IntelÂ® Extended Memory 64 Technology Software Developer's Guide

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#PF(fault-code)#AC(0)For a page fault.If alignment checking is enabled and an unaligned memory reference is made.Compatibility Mode ExceptionsSame as protected mode exceptions.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a non-canonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code) For a page fault.#NMIf TS in CR0 is set.#XM If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.#UD If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE2 is 0.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while thecurrent privilege level is 3.2-120 Vol. 1
CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to ScalarSingle-Precision Floating-Point ValueOpcode Instruction 64-Bit Mode Compat/Leg DescriptionModeF2 0F 5A /r CVTSD2SS xmm1, xmm2/m64 Valid Valid Convert one double-precision floatingpointvalue in xmm2/m64 to one singleprecisionfloating-point value in xmm1.IA-32e Mode OperationEnables access to XMM8-XMM15.SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code) For a page fault.#NMIf TS in CR0 is set.#XM If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.#UD If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE2 is 0.#AC(0)If alignment checking is enabled and an unaligned memory reference is made while thecurrent privilege level is 3.Real-Address Mode Exceptions#GP(0)If any part of the operand lies outside the effective address space from 0 to FFFFH.#NMIf TS in CR0 is set.#XM If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.#UD If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0.If EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag SSE2 is 0.Virtual-8086 Mode ExceptionsSame exceptions as in Real Address Mode#PF(fault-code)#AC(0)For a page fault.If alignment checking is enabled and an unaligned memory reference is made.Vol. 1 2-121
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Intel ® Extended Memory 64 Technol
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1.6.9.1. Call Gates. . . . . . . .
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FSUB/FSUBP/FISUB—Subtract . . . .
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PADDSB/PADDSW—Add Packed Signed I
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-xii Vol. 1
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ModeIA-32emodeOperatingSystemRequir
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1.3. REGISTER-SET CHANGESThis secti
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Table 1-4 IA32_EFER Bit Description
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IA-32e sub-modeTable 1-8 64-Bit Ext
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REX PREFIX0100WR0BOpcodemod!=11ModR
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1.4.2.4. Direct Memory-Offset MOVsI
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The 64-bit default operation-size e
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1.6.2. Register Settings and IA-32e
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1.6.3.4. Compatibility ModeCompatib
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• When in compatibility mode, FS
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Prior to activating IA-32e mode, PA
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Table 1-22 through Table 1-24 shows
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Table 1-26 Reserved Bit CheckingMod
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• Bits 29:21 index into the 512-e
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Only 64-bit mode call gates can be
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Although the hardware task-switchin
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Table 1-39 IA-32e Mode Interrupt an
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If the IST index for an interrupt g
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1-38 Vol. 1
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• ib, iw, id, io — A 1-byte (ib
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• m16:16, m16:32 & m16:64 —A me
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which is either 16, 32 or 64-bits.
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2.1.3.1. IA-32e Mode OperationThe s
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2.1.10. SIMD Floating-Point Excepti
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AAD—ASCII Adjust AX Before Divisi
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AAS—ASCII Adjust AL After Subtrac
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Real-Address Mode Exceptions#GPIf a
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64-Bit Mode Exceptions#SS(0)If a me
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#PF(fault-code)#NM#UDFor a page fau
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BOUND—Check Array Index Against B
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BSF—Bit Scan ForwardOpcode Instru
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BSWAP—Byte SwapOpcode Instruction
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#AC(0)If alignment checking is enab
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#GP(0)#PF(fault-code)#AC(0)If the m
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#PF(fault-code)#AC(0)If a page faul
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Compatibility Mode ExceptionsSame a
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CDQ—Convert Double to QuadSee ent
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CLD—Clear Direction FlagOpcode In
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CLI—Clear Interrupt FlagOpcode In
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CMC—Complement Carry FlagOpcode I
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Opcode Instruction 64-Bit Mode Comp
Page 119 and 120: CMP—Compare Two OperandsOpcode In
Page 121 and 122: CMPPD—Compare Packed Double-Preci
Page 123 and 124: CMPPS—Compare Packed Single-Preci
Page 125 and 126: CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Comp
Page 127 and 128: CMPSD—Compare Scalar Double-Preci
Page 129 and 130: CMPSS—Compare Scalar Single-Preci
Page 131 and 132: CMPXCHG—Compare and ExchangeOpcod
Page 133 and 134: CMPXCHG8B/CMPXCHG16B—Compare and
Page 135 and 136: COMISD—Compare Scalar Ordered Dou
Page 137 and 138: COMISS—Compare Scalar Ordered Sin
Page 139 and 140: CPUID—CPU IdentificationOpcode In
Page 141 and 142: Initial EAXValue80000005H80000006H8
Page 143 and 144: Table 2-8 CPUID Feature Information
Page 145 and 146: • The most significant bit (bit 3
Page 147 and 148: Table 2-10 Brand String Offsets (Co
Page 149 and 150: CVTDQ2PD—Convert Packed Doublewor
Page 151 and 152: CVTDQ2PS—Convert Packed Doublewor
Page 153 and 154: CVTPD2DQ—Convert Packed Double-Pr
Page 155 and 156: CVTPD2PI—Convert Packed Double-Pr
Page 157 and 158: CVTPD2PS—Covert Packed Double-Pre
Page 159 and 160: CVTPI2PD—Convert Packed Doublewor
Page 161 and 162: CVTPI2PS—Convert Packed Doublewor
Page 163 and 164: CVTPS2DQ—Convert Packed Single-Pr
Page 165 and 166: CVTPS2PD—Covert Packed Single-Pre
Page 167 and 168: CVTPS2PI—Convert Packed Single-Pr
Page 169: CVTSD2SI—Convert Scalar Double-Pr
Page 173 and 174: CVTSI2SD—Convert Doubleword Integ
Page 175 and 176: CVTSI2SS—Convert Doubleword Integ
Page 177 and 178: CVTSS2SD—Convert Scalar Single-Pr
Page 179 and 180: CVTSS2SI—Convert Scalar Single-Pr
Page 181 and 182: CVTTPD2PI—Convert with Truncation
Page 183 and 184: CVTTPD2DQ—Convert with Truncation
Page 185 and 186: CVTTPS2DQ—Convert with Truncation
Page 187 and 188: CVTTPS2PI—Convert with Truncation
Page 189 and 190: CVTTSD2SI—Convert with Truncation
Page 191 and 192: CVTTSS2SI—Convert with Truncation
Page 193 and 194: CWD/CDQ/CQQ—Convert Word to Doubl
Page 195 and 196: DAS—Decimal Adjust AL after Subtr
Page 197 and 198: 64-Bit Mode Exceptions#SS(0)If a me
Page 199 and 200: Virtual-8086 Mode Exceptions#DE If
Page 209 and 210: ENTER—Make Stack Frame for Proced
Page 211 and 212: FABS—Absolute ValueOpcode Instruc
Page 213 and 214: Real-Address Mode Exceptions#GPIf a
Page 217 and 218: Virtual-8086 Mode Exceptions#GP(0)I
Page 219 and 220: FCLEX/FNCLEX—Clear ExceptionsOpco
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FCOM/FCOMP/FCOMPP—Compare Floatin
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FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Comp
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FDECSTP—Decrement Stack-Top Point
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FICOM/FICOMP—Compare IntegerOpcod
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FILD—Load IntegerOpcode Instructi
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FINCSTP—Increment Stack-Top Point
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FIST/FISTP—Store IntegerOpcode In
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FISTTP—Store Integer with Truncat
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FLD—Load Floating Point ValueOpco
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FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLD
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FPATAN—Partial ArctangentOpcode I
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FPREM1—Partial RemainderOpcode In
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FRNDINT—Round to IntegerOpcode In
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Virtual-8086 Mode Exceptions#GP(0)I
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FSIN—SineOpcode Instruction 64-Bi
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FSQRT—Square RootOpcode Instructi
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Protected Mode Exceptions#GP(0)If a
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Protected Mode Exceptions#GP(0)If a
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FUCOM/FUCOMP/FUCOMPP—Unordered Co
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FXAM—ExamineOpcode Instruction 64
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FXRSTOR—Restore x87 FPU, MMX, SSE
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FXSAVE—Save x87 FPU, MMX, SSE, an
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XMM0 throughXMM7XMM registers (128
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Table 2-14 Layout of the 64-bit FXS
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Protected Mode Exceptions#GP(0)For
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FXTRACT—Extract Exponent and Sign
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FYL2XP1—Compute y ∗ log 2 (x +1
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HSUBPD—Horizontal Subtract Packed
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HSUBPS—Horizontal Subtract Packed
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IDIV—Signed DivideOpcode Instruct
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IMUL—Signed MultiplyOpcode Instru
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IN—Input from PortOpcode Instruct
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INVD—Invalidate Internal CachesOp
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IRET/IRETD—Interrupt ReturnOpcode
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Jcc—Jump if Condition Is MetOpcod
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Opcode Instruction 64-Bit Mode Comp
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#SS(0)#NP (selector)#PF(fault-code)
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LAHF—Load Status Flags into AH Re
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LDDQU—Load Unaligned Double Quadw
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LDMXCSR—Load MXCSR RegisterOpcode
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LDS/LES/LFS/LGS/LSS—Load Far Poin
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LEA—Load Effective AddressOpcode
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LES—Load Full PointerSee entry fo
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LFS—Load Full PointerSee entry fo
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LGS—Load Full PointerSee entry fo
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LMSW—Load Machine Status WordOpco
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LODS/LODSB/LODSW/LODSD/LODSQ—Load
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LOOP/LOOPcc—Loop According to ECX
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LSS—Load Full PointerSee entry fo
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