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Intel® Extended Memory 64 Technology Software Developer's Guide

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2.1.3.1. IA-32e Mode OperationThe section “IA-32e Mode Operation” summarizes instruction behavior in <strong>64</strong>-bit mode that differs from legacy IA-32modes.2.1.4. Flags AffectedThe “Flags Affected” section lists the flags in the EFLAGS register that are affected by the instruction. When a flag iscleared, it is equal to 0; when it is set, it is equal to 1. The arithmetic and logical instructions usually assign values tothe status flags in a uniform manner (see Appendix A, EFLAGS Cross-Reference, in the IA-32 Intel Architecture <strong>Software</strong>Developer’s Manual, Volume 1). Non-conventional assignments are described in the “Operation” section. Thevalues of flags listed as undefined may be changed by the instruction in an indeterminate manner. Flags that are notlisted are unchanged by the instruction.2.1.5. FPU Flags AffectedThe floating-point instructions have an “FPU Flags Affected” section that describes how each instruction can affectthe four condition code flags of the FPU status word.2.1.6. Protected Mode ExceptionsThe “Protected Mode Exceptions” section lists the exceptions that can occur when the instruction is executed inprotected mode and the reasons for the exceptions. Each exception is given a mnemonic that consists of a pound sign(#) followed by two letters and an optional error code in parentheses. For example, #GP(0) denotes a general protectionexception with an error code of 0. Table 2-2 associates each two-letter mnemonic with the corresponding interruptvector number and exception name. See Chapter 5, Interrupt and Exception Handling, in the IA-32 Intel Architecture<strong>Software</strong> Developer’s Manual, Volume 3, for a detailed description of the exceptions.Application programmers should consult the documentation provided with their operating systems to determine theactions taken when exceptions occur.VectorNo. Name SourceTable 2-2 Interrupt VectorsProtectedModeRealAddressModeVirtual8086Mode<strong>64</strong>-Bit Mode0 #DE—Divide Error DIV and IDIV instructions. Yes Yes Yes Yes1 #DB—Debug Any code or data reference. Yes Yes Yes Yes3 #BP—Breakpoint INT 3 instruction. Yes Yes Yes Yes4 #OF—Overflow INTO instruction. Yes Yes Yes Yes5 #BR—BOUND RangeExceededBOUND instruction. Yes Yes Yes Reserved6 #UD—Invalid Opcode(Undefined Opcode)7 #NM—Device NotAvailable (No MathCoprocessor)UD2 instruction or reservedopcode.Floating-point or WAIT/FWAITinstruction.8 #DF—Double Fault Any instruction that cangenerate an exception, an NMI,or an INTR.Yes Yes Yes YesYes Yes Yes YesYes Yes Yes Yes10 #TS—Invalid TSS Task switch or TSS access. Yes Reserved Yes Yes11 #NP—Segment NotPresentLoading segment registers oraccessing system segments.Yes Reserved Yes Yes2-8 Vol. 1

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