Intel® Extended Memory 64 Technology Software Developer's Guide

1.6.5.3. Overall Page ProtectionThe addition of incremental layers of paging necessitates changes by applying the same IA-32 methodology on the R/W and U/S flags to four levels of the page tables. Table 1-25 shows IA-32e mode paging protection.Table 1-25 IA-32e Mode Page Level Protection MatrixPrivilege (U/S bit, bit 2) Access Type (R/W bit, bit 1 Combined EffectsPML4 PDP PDE PTE PML4 PDP PDE PTEUser User User User RO * * * User ROUser User User User * RO * * User ROUser User User User * * RO * User ROUser User User User * * * RO User ROUser User User User R/W R/W R/W R/W User R/WSuper * * * * * * * Super R/W* Super * * * * * * Super R/W* * Super * * * * * Super R/W* * * Super * * * * Super R/WThere are two basic rules for combining the privilege levels and access types from multiple levels of page entrieswithin a page walk. These are:1. The most privilege mode of the page entries within the page walk will be used. (for example, a page has asupervisor privilege level if the U/S bit is cleared in any of its page entries).2. The most restrictive access type of the page entries with the page walk will be used (for example, a page has aread-only access type if the R/W bit is cleared in any of the page entries).1.6.5.4. Reserved Bit CheckingThe processor will enforce reserved bit checking on the following paging mode specific bits. Table 1-26 shows thereserved bits that are checked. In legacy paging modes of Table 1-26:• Non-PAE 4KB paging: 4KB-page only paging (CR4.PAE = 0, CR4.PSE = 0)• PSE-36: 4KB and 4MB pages (CR4.PAE = 0, CR4.PSE = 1)• PAE: 4KB and 2MB pages (CR4.PAE = 1, CR4.PSE = x)Vol. 1 1-25