IntelÂ® Extended Memory 64 Technology Software Developer's Guide

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AAS—ASCII Adjust AL After SubtractionOpcode Instruction 64-Bit Mode Compat/Leg DescriptionMode3F AAS Inv. Valid ASCII adjust AL after subtractionFlags AffectedThe AF and CF flags are set to 1 if there is a decimal borrow; otherwise, they are cleared to 0. The OF, SF, ZF, and PFflags are undefined.IA-32e Mode OperationInstruction is invalid in 64-bit mode.Protected Mode ExceptionsNoneReal-Address Mode ExceptionsNoneVirtual-8086 Mode ExceptionsNoneCompatibility Mode ExceptionsNone64-Bit Mode Exceptions#UDIf in 64-bit mode.2-14 Vol. 1
ADC—Add with CarryOpcode Instruction 64-Bit Mode Compat/Leg DescriptionMode14 ib ADC AL,imm8 Valid Valid Add with carry imm8 to AL15 iw ADC AX,imm16 Valid Valid Add with carry imm16 to AX15 id ADC EAX,imm32 Valid Valid Add with carry imm32 to EAXREX.W + 15 id ADC RAX,imm32 Valid N.E. Add with carry imm32 sign extended to 64-bitsto RAX80 /2 ib ADC r/m8,imm8 Valid Valid Add with carry imm8 to r/m8REX + 80 /2 ib ADC r/m8*,imm8 Valid N.E. Add with carry imm8 to r/m881 /2 iw ADC r/m16,imm16 Valid Valid Add with carry imm16 to r/m1681 /2 id ADC r/m32,imm32 Valid Valid Add with CF imm32 to r/m32REX.W + 81 /2 id ADC r/m64,imm32 Valid N.E. Add with CF imm32 sign extended to 64-bits tor/m6483 /2 ib ADC r/m16,imm8 Valid Valid Add with CF sign-extended imm8 to r/m1683 /2 ib ADC r/m32,imm8 Valid Valid Add with CF sign-extended imm8 into r/m32REX.W + 83 /2 ib ADC r/m64,imm8 Valid N.E. Add with CF sign-extended imm8 into r/m6410 /r ADC r/m8,r8 Valid Valid Add with carry byte register to r/m8REX + 10 /r ADC r/m8*,r8* Valid N.E. Add with carry byte register to r/m6411 /r ADC r/m16,r16 Valid Valid Add with carry r16 to r/m1611 /r ADC r/m32,r32 Valid Valid Add with CF r32 to r/m32REX.W + 11 /r ADC r/m64,r64 Valid N.E. Add with CF r64 to r/m6412 /r ADC r8,r/m8 Valid Valid Add with carry r/m8 to byte registerREX + 12 /r ADC r8*,r/m8* Valid N.E. Add with carry r/m64 to byte register13 /r ADC r16,r/m16 Valid Valid Add with carry r/m16 to r1613 /r ADC r32,r/m32 Valid Valid Add with CF r/m32 to r32REX.W + 13 /r ADC r64,r/m64 Valid N.E. Add with CF r/m64 to r64* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if an REX prefix is used: AH, BH, CH, DH. Alsorefer to Section 1.4.2.2.Flags AffectedThe OF, SF, ZF, AF, CF, and PF flags are set according to the result.IA-32e Mode OperationPromoted to 64-bits.Default Operation Size is 32 bitsEnables access to new registers R8-R15.Protected Mode Exceptions#GP(0)#SS(0)#PF(fault-code)#AC(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and it contains a null segmentselector.If a memory operand effective address is outside the SS segment limit.If a page fault occurs.If alignment checking is enabled and an unaligned memory reference is made while thecurrent privilege level is 3.Vol. 1 2-15
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Intel ® Extended Memory 64 Technol
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1.6.9.1. Call Gates. . . . . . . .
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FSUB/FSUBP/FISUB—Subtract . . . .
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PADDSB/PADDSW—Add Packed Signed I
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-xii Vol. 1
Page 14 and 15: ModeIA-32emodeOperatingSystemRequir
Page 16 and 17: 1.3. REGISTER-SET CHANGESThis secti
Page 18 and 19: Table 1-4 IA32_EFER Bit Description
Page 20 and 21: IA-32e sub-modeTable 1-8 64-Bit Ext
Page 22 and 23: REX PREFIX0100WR0BOpcodemod!=11ModR
Page 24 and 25: 1.4.2.4. Direct Memory-Offset MOVsI
Page 26 and 27: The 64-bit default operation-size e
Page 28 and 29: 1.6.2. Register Settings and IA-32e
Page 30 and 31: 1.6.3.4. Compatibility ModeCompatib
Page 32 and 33: • When in compatibility mode, FS
Page 34 and 35: Prior to activating IA-32e mode, PA
Page 36 and 37: Table 1-22 through Table 1-24 shows
Page 38 and 39: Table 1-26 Reserved Bit CheckingMod
Page 40 and 41: • Bits 29:21 index into the 512-e
Page 42 and 43: Only 64-bit mode call gates can be
Page 44 and 45: Although the hardware task-switchin
Page 46 and 47: Table 1-39 IA-32e Mode Interrupt an
Page 48 and 49: If the IST index for an interrupt g
Page 50 and 51: 1-38 Vol. 1
Page 52 and 53: • ib, iw, id, io — A 1-byte (ib
Page 54 and 55: • m16:16, m16:32 & m16:64 —A me
Page 56 and 57: which is either 16, 32 or 64-bits.
Page 58 and 59: 2.1.3.1. IA-32e Mode OperationThe s
Page 60 and 61: 2.1.10. SIMD Floating-Point Excepti
Page 62 and 63: AAD—ASCII Adjust AX Before Divisi
Page 66 and 67: Real-Address Mode Exceptions#GPIf a
Page 70 and 71: 64-Bit Mode Exceptions#SS(0)If a me
Page 84 and 85: #PF(fault-code)#NM#UDFor a page fau
Page 92 and 93: BOUND—Check Array Index Against B
Page 94 and 95: BSF—Bit Scan ForwardOpcode Instru
Page 96 and 97: BSWAP—Byte SwapOpcode Instruction
Page 98 and 99: #AC(0)If alignment checking is enab
Page 100 and 101: #GP(0)#PF(fault-code)#AC(0)If the m
Page 102 and 103: #PF(fault-code)#AC(0)If a page faul
Page 104: 64-Bit Mode Exceptions#SS(0)If a me
Page 107 and 108: Compatibility Mode ExceptionsSame a
Page 109 and 110: CDQ—Convert Double to QuadSee ent
Page 111 and 112: CLD—Clear Direction FlagOpcode In
Page 113 and 114: CLI—Clear Interrupt FlagOpcode In
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CMC—Complement Carry FlagOpcode I
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Opcode Instruction 64-Bit Mode Comp
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CMP—Compare Two OperandsOpcode In
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CMPPD—Compare Packed Double-Preci
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CMPPS—Compare Packed Single-Preci
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CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Comp
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CMPSD—Compare Scalar Double-Preci
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CMPSS—Compare Scalar Single-Preci
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CMPXCHG—Compare and ExchangeOpcod
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CMPXCHG8B/CMPXCHG16B—Compare and
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COMISD—Compare Scalar Ordered Dou
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COMISS—Compare Scalar Ordered Sin
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CPUID—CPU IdentificationOpcode In
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Initial EAXValue80000005H80000006H8
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Table 2-8 CPUID Feature Information
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• The most significant bit (bit 3
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Table 2-10 Brand String Offsets (Co
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CVTDQ2PD—Convert Packed Doublewor
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CVTDQ2PS—Convert Packed Doublewor
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CVTPD2DQ—Convert Packed Double-Pr
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CVTPD2PI—Convert Packed Double-Pr
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CVTPD2PS—Covert Packed Double-Pre
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CVTPI2PD—Convert Packed Doublewor
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CVTPI2PS—Convert Packed Doublewor
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CVTPS2DQ—Convert Packed Single-Pr
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CVTPS2PD—Covert Packed Single-Pre
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CVTPS2PI—Convert Packed Single-Pr
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CVTSD2SI—Convert Scalar Double-Pr
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CVTSD2SS—Convert Scalar Double-Pr
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CVTSI2SD—Convert Doubleword Integ
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CVTSI2SS—Convert Doubleword Integ
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CVTSS2SD—Convert Scalar Single-Pr
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CVTSS2SI—Convert Scalar Single-Pr
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CVTTPD2PI—Convert with Truncation
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CVTTPD2DQ—Convert with Truncation
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CVTTPS2DQ—Convert with Truncation
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CVTTPS2PI—Convert with Truncation
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CVTTSD2SI—Convert with Truncation
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CVTTSS2SI—Convert with Truncation
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CWD/CDQ/CQQ—Convert Word to Doubl
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DAS—Decimal Adjust AL after Subtr
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64-Bit Mode Exceptions#SS(0)If a me
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Virtual-8086 Mode Exceptions#DE If
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ENTER—Make Stack Frame for Proced
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FABS—Absolute ValueOpcode Instruc
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Real-Address Mode Exceptions#GPIf a
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Virtual-8086 Mode Exceptions#GP(0)I
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FCLEX/FNCLEX—Clear ExceptionsOpco
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FCOM/FCOMP/FCOMPP—Compare Floatin
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FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Comp
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FDECSTP—Decrement Stack-Top Point
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FICOM/FICOMP—Compare IntegerOpcod
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FILD—Load IntegerOpcode Instructi
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FINCSTP—Increment Stack-Top Point
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FIST/FISTP—Store IntegerOpcode In
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FISTTP—Store Integer with Truncat
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FLD—Load Floating Point ValueOpco
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FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLD
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Compatibility Mode ExceptionsSame a
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FPATAN—Partial ArctangentOpcode I
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FPREM1—Partial RemainderOpcode In
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FRNDINT—Round to IntegerOpcode In
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FSIN—SineOpcode Instruction 64-Bi
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FSQRT—Square RootOpcode Instructi
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Protected Mode Exceptions#GP(0)If a
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Protected Mode Exceptions#GP(0)If a
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FUCOM/FUCOMP/FUCOMPP—Unordered Co
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FXAM—ExamineOpcode Instruction 64
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FXRSTOR—Restore x87 FPU, MMX, SSE
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FXSAVE—Save x87 FPU, MMX, SSE, an
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XMM0 throughXMM7XMM registers (128
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Table 2-14 Layout of the 64-bit FXS
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Protected Mode Exceptions#GP(0)For
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FXTRACT—Extract Exponent and Sign
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FYL2XP1—Compute y ∗ log 2 (x +1
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HSUBPD—Horizontal Subtract Packed
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HSUBPS—Horizontal Subtract Packed
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IDIV—Signed DivideOpcode Instruct
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IMUL—Signed MultiplyOpcode Instru
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IN—Input from PortOpcode Instruct
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Compatibility Mode ExceptionsSame a
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INVD—Invalidate Internal CachesOp
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IRET/IRETD—Interrupt ReturnOpcode
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Jcc—Jump if Condition Is MetOpcod
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Opcode Instruction 64-Bit Mode Comp
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#SS(0)#NP (selector)#PF(fault-code)
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LAHF—Load Status Flags into AH Re
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LDDQU—Load Unaligned Double Quadw
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LDMXCSR—Load MXCSR RegisterOpcode
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LDS/LES/LFS/LGS/LSS—Load Far Poin
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LEA—Load Effective AddressOpcode
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LES—Load Full PointerSee entry fo
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LFS—Load Full PointerSee entry fo
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LGS—Load Full PointerSee entry fo
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LMSW—Load Machine Status WordOpco
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LODS/LODSB/LODSW/LODSD/LODSQ—Load
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LOOP/LOOPcc—Loop According to ECX
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LSS—Load Full PointerSee entry fo
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IntelÂ® Extended Memory 64 Technology Software Developer's Guide

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