Intel® Extended Memory 64 Technology Software Developer's Guide

• Bits 29:21 index into the 512-entry page-directory table (PDE).• Bits 20:12 index into the 512-entry page table (PTE).• Bits 11:0 provide the byte offset into the physical page.Table 1-29 4KB Page Translation63:48 47:39 38:30 29:21 20:12 11:0Sign Extend Page Map Level 4Table Offset(PML4E)Page DirectoryPointer Offset(PDPE)Page DirectoryTable Offset(PDE)Page Table Offset(PTE)Page OffsetPML4E PDPE PDE PTE PhysicalAddressCR3Table 1-30 CR3 Page Directory Pointer Offset63:40 39:12 11:0Page Directory Pointer Offset2MByte pages are enabled by setting the PDE page size flag to 1 (PDE.PS = 1). Because the first implementation ofthe Intel EM64T supports a maximum 48 bits of linear address, this paging option supports 2 27 2MByte pages spanninga linear-address space of 2 48 bytes (256 terabytes).The 48-bit linear address is broken up into four fields to index into the 3-level paging structure, as follows:• Bits 47:39 index into the 512-entry page map level-4 table.• Bits 38:30 index into the 512-entry page-directory pointer table.• Bits 29:21 index into the 512-entry page-directory table.• Bits 20:0 provide the byte offset into the physical page.1.6.9. Privilege-Level Transitions and Far TransfersThe 64-bit extensions provide three mechanisms for changing privilege levels:• Call gates and interrupt gates• SYSCALL and SYSRET instructions• SYSENTER and SYSEXIT instructions1-28 Vol. 1