Intel® Extended Memory 64 Technology Software Developer's Guide

1.7. GENERAL RULES FOR 64-BIT MODEIn 64-bit mode, the following general rules apply to changes in instructions and their operands:• If an instruction's operand size in legacy mode (16-bit or 32-bit) depends on the effective operand size(dependent on CS.D and prefix overrides); operand-size choices are extended in 64-bit mode from 16-bit and 32-bit to include 64 bits, or the operand size is fixed at a size that supports 64-bit operands. Such instructions are saidto be ‘promoted to 64 bits’. However, byte-operand opcodes of such instructions are not promoted.• As stated above, the byte-operand opcodes of promoted instructions are not usually promoted. Those instructionscontinue to operate only on bytes.• If an instruction's operand size is fixed in legacy mode (independent of CS.D and prefix overrides), that operandsize is usually fixed at the same size in 64-bit mode. For example, CPUID operates on the same-size operands inlegacy mode and 64-bit mode. There are some exceptions.• Operations on 32-bit operands in 64-bit mode zero-extend the high 32 bits of 64-bit GPR destination registers.• When operating on 8-bit (or 16-bit) operands in 64-bit mode, the high 56 (or 48) bits of 64-bit GPR destinationregisters are unchanged.• When the operand size is 64 bits, the shift and rotate instructions use one additional bit (6 bits total) to specifyshift-count or rotate-count, allowing 64-bit shifts and rotates.• The maximum size of immediate operands remains 32 bits, except that 64-bit immediates can be moved to 64-bitGPRs. When the operand size is 64 bits, immediates are sign-extended to 64 bits prior to using them.• Branch-address displacements remains 8 bits or 32 bits, but they are sign-extended to 64 bits prior to using them.• When the processor makes transitions from 64-bit mode to compatibility or legacy modes, it does not preservethe upper 32 bits of the 64-bit GPRs. In compatibility or legacy mode, only the lower 32 bits of the GPRS aredefined.1.7.1. Other Guidelines• In the initial implementation of Intel EM64T, an operand-size prefix (66H) is ignored when used in 64-bit modewith a near branch. In 64-bit mode, a near branch uses 32-bit displacement (the instruction pointer is advanced toa linear address that is the next sequential instruction offset by a 32 bit displacement, sign extended to 64-bit).Software must not rely on this behavior as future implementations may be different.• In 64-bit mode, when the value of the source operand for BSR/BSF is 0, the upper 32 bits of the registers arecleared.Vol. 1 1-37