Single-Chip Low Cost Low Power RF-Transceiver (Rev. A)

CC2500burst bit in the address header. The addresssets the start address in an internal addresscounter. This counter is incremented by oneeach new byte (every 8 clock pulses). Theburst access is either a read or a write accessand must be terminated by setting CSn high.For register addresses in the range 0x30-0x3D, the “burst” bit is used to select betweenstatus registers and command strobes (seebelow). The status registers can only be read.Burst read is not available for status registers,so they must be read one at a time.10.3 SPI ReadWhen reading register fields over the SPIinterface while the register fields are updatedby the radio hardware (e.g. MARCSTATE orTXBYTES), there is a small, but finite,probability that a single read from the registeris being corrupt. As an example, theprobability of any single read from TXBYTESbeing corrupt, assuming the maximum datarate is used, is approximately 80 ppm. Refer tothe CC2500 Errata Note for more details.10.4 Command StrobesCommand strobes may be viewed as singlebyte instructions to CC2500. By addressing acommand strobe register, internal sequenceswill be started. These commands are used todisable the crystal oscillator, enable receivemode, enable wake-on-radio etc. The 14command strobes are listed in Table 34 onpage 51.The command strobe registers are accessedin the same way as for a register writeoperation, but no data is transferred. That is,only the R/W bit (set to 0), burst access (set to0) and the six address bits (in the range 0x30through 0x3D) are written.When writing command strobes, the statusbyte is sent on the SO pin.A command strobe may be followed by anyother SPI access without pulling CSn high.After issuing an SRES command strobe thenext command strobe can be issued when theSO pin goes low as shown in Figure 9. Thecommand strobes are executed immediately,with the exception of the SPWD and the SXOFFstrobes that are executed when CSn goeshigh.Figure 9: SRES command strobe10.5 FIFO AccessThe 64-byte TX FIFO and the 64-byte RXFIFO are accessed through the 0x3F address.When the read/write bit is zero, the TX FIFO isaccessed, and the RX FIFO is accessed whenthe read/write bit is one.The TX FIFO is write-only, while the RX FIFOis read-only.The burst bit is used to determine if FIFOaccess is single byte or a burst access. Thesingle byte access method expects addresswith burst bit set to zero and one data byte.After the data byte a new address is expected;hence, CSn can remain low. The burst accessmethod expects one address byte and thenconsecutive data bytes until terminating theaccess by setting CSn high.The following header bytes access the FIFOs:• 0x3F: Single byte access to TX FIFO• 0x7F: Burst access to TX FIFO• 0xBF: Single byte access to RX FIFO• 0xFF: Burst access to RX FIFOWhen writing to the TX FIFO, the status byte(see Section 10.1) is output for each new databyte on SO, as shown in Figure 7. This statusbyte can be used to detect TX FIFO underflowwhile writing data to the TX FIFO. Note thatthe status byte contains the number of bytesfree before writing the byte in progress to theTX FIFO. When the last byte that fits in the TXFIFO is transmitted to the SI pin, the statusbyte received concurrently on the SO pin willindicate that one byte is free in the TX FIFO.The transmit FIFO may be flushed by issuing aSFTX command strobe. Similarly, a SFRXcommand strobe will flush the receive FIFO. ASFTX or SFRX command strobe can only beissued in the IDLE, TXFIFO_UNDERLOW orRXFIFO_OVERFLOW state. Both FIFOs areflushed when going to the SLEEP state.PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 22 of 83