Single-Chip Low Cost Low Power RF-Transceiver (Rev. A)

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CC2500burst bit in the address header. The addresssets the start address in an internal addresscounter. This counter is incremented by oneeach new byte (every 8 clock pulses). Theburst access is either a read or a write accessand must be terminated by setting CSn high.For register addresses in the range 0x30-0x3D, the “burst” bit is used to select betweenstatus registers and command strobes (seebelow). The status registers can only be read.Burst read is not available for status registers,so they must be read one at a time.10.3 SPI ReadWhen reading register fields over the SPIinterface while the register fields are updatedby the radio hardware (e.g. MARCSTATE orTXBYTES), there is a small, but finite,probability that a single read from the registeris being corrupt. As an example, theprobability of any single read from TXBYTESbeing corrupt, assuming the maximum datarate is used, is approximately 80 ppm. Refer tothe CC2500 Errata Note for more details.10.4 Command StrobesCommand strobes may be viewed as singlebyte instructions to CC2500. By addressing acommand strobe register, internal sequenceswill be started. These commands are used todisable the crystal oscillator, enable receivemode, enable wake-on-radio etc. The 14command strobes are listed in Table 34 onpage 51.The command strobe registers are accessedin the same way as for a register writeoperation, but no data is transferred. That is,only the R/W bit (set to 0), burst access (set to0) and the six address bits (in the range 0x30through 0x3D) are written.When writing command strobes, the statusbyte is sent on the SO pin.A command strobe may be followed by anyother SPI access without pulling CSn high.After issuing an SRES command strobe thenext command strobe can be issued when theSO pin goes low as shown in Figure 9. Thecommand strobes are executed immediately,with the exception of the SPWD and the SXOFFstrobes that are executed when CSn goeshigh.Figure 9: SRES command strobe10.5 FIFO AccessThe 64-byte TX FIFO and the 64-byte RXFIFO are accessed through the 0x3F address.When the read/write bit is zero, the TX FIFO isaccessed, and the RX FIFO is accessed whenthe read/write bit is one.The TX FIFO is write-only, while the RX FIFOis read-only.The burst bit is used to determine if FIFOaccess is single byte or a burst access. Thesingle byte access method expects addresswith burst bit set to zero and one data byte.After the data byte a new address is expected;hence, CSn can remain low. The burst accessmethod expects one address byte and thenconsecutive data bytes until terminating theaccess by setting CSn high.The following header bytes access the FIFOs:• 0x3F: Single byte access to TX FIFO• 0x7F: Burst access to TX FIFO• 0xBF: Single byte access to RX FIFO• 0xFF: Burst access to RX FIFOWhen writing to the TX FIFO, the status byte(see Section 10.1) is output for each new databyte on SO, as shown in Figure 7. This statusbyte can be used to detect TX FIFO underflowwhile writing data to the TX FIFO. Note thatthe status byte contains the number of bytesfree before writing the byte in progress to theTX FIFO. When the last byte that fits in the TXFIFO is transmitted to the SI pin, the statusbyte received concurrently on the SO pin willindicate that one byte is free in the TX FIFO.The transmit FIFO may be flushed by issuing aSFTX command strobe. Similarly, a SFRXcommand strobe will flush the receive FIFO. ASFTX or SFRX command strobe can only beissued in the IDLE, TXFIFO_UNDERLOW orRXFIFO_OVERFLOW state. Both FIFOs areflushed when going to the SLEEP state.PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 22 of 83
CC250010.6 PATABLE AccessThe 0x3E address is used to access thePATABLE, which is used for selecting PApower control settings. The SPI expects up toeight data bytes after receiving the address.By programming the PATABLE, controlled PApower ramp-up and ramp-down can beachieved. See Section 24 on page 42 foroutput power programming details.The PATABLE is an 8-byte table that definesthe PA control settings to use for each of theeight PA power values (selected by the 3-bitvalue FREND0.PA_POWER). The table iswritten and read from the lowest setting (0) tothe highest (7), one byte at a time. An indexcounter is used to control the access to thetable. This counter is incremented each time abyte is read or written to the table, and set tothe lowest index when CSn is high. When thehighest value is reached the counter restartsat 0.The access to the PATABLE is either singlebyte or burst access depending on the burstbit. When using burst access the index counterwill count up; when reaching 7 the counter willrestart at 0. The read/write bit controls whetherthe access is a write access (R/W=0) or a readaccess (R/W=1).If one byte is written to the PATABLE and thisvalue is to be read out then CSn must be sethigh before the read access in order to set theindex counter back to zero.Note that the content of the PATABLE is lostwhen entering the SLEEP state, except for thefirst byte (index 0).11 Microcontroller Interface and Pin ConfigurationIn a typical system, CC2500 will interface to amicrocontroller. This microcontroller must beable to:• Program CC2500 into different modes• Read and write buffered data• Read back status information via the 4-wireSPI-bus configuration interface (SI, SO,SCLK and CSn)11.1 Configuration InterfaceThe microcontroller uses four I/O pins for theSPI configuration interface (SI, SO, SCLK andCSn). The SPI is described in Section 10 onpage 19.11.2 General Control and Status PinsThe CC2500 has two dedicated configurablepins and one shared pin that can outputinternal status information useful for controlsoftware. These pins can be used to generateinterrupts on the MCU. See Section 28 onpage 46 for more details on the signals thatcan be programmed. The dedicated pins arecalled GDO0 and GDO2. The shared pin is theSO pin in the SPI interface. The default settingfor GDO1/SO is 3-state output. By selectingany other of the programming options theGDO1/SO pin will become a generic pin. WhenCSn is low, the pin will always function as anormal SO pin.In the synchronous and asynchronous serialmodes, the GDO0 pin is used as a serial TXdata input pin while in transmit mode.The GDO0 pin can also be used for an on-chipanalog temperature sensor. By measuring thevoltage on the GDO0 pin with an external ADC,the temperature can be calculated.Specifications for the temperature sensor arefound in Section 4.7 on page 12.With default PTEST register setting (0x7F) thetemperature sensor output is only availablewhen the frequency synthesizer is enabled(e.g. the MANCAL, FSTXON, RX and TXstates). It is necessary to write 0xBF to thePTEST register to use the analog temperaturesensor in the IDLE state. Before leaving theIDLE state, the PTEST register should berestored to its default value (0x7F).11.3 Optional Radio Control FeatureThe CC2500 has an optional way of controllingthe radio, by reusing SI, SCLK and CSn fromthe SPI interface. This feature allows for asimple three-pin control of the major states ofthe radio: SLEEP, IDLE, RX and TX.This optional functionality is enabled with theMCSM0.PIN_CTRL_EN configuration bit.State changes are commanded as follows:When CSn is high the SI and SCLK is set tothe desired state according to Table 18. WhenCSn goes low the state of SI and SCLK islatched and a command strobe is generatedPRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 23 of 83
Page 1 and 2: CC2500CC2500Single Chip Low Cost Lo
Page 3 and 4: CC2500Table of ContentsAPPLICATIONS
Page 5 and 6: CC250033 ORDERING INFORMATION......
Page 7 and 8: CC25004 Electrical Specifications4.
Page 9 and 10: CC2500Parameter Min Typ Max Unit Co
Page 11 and 12: CC25004.5 Low Power RC OscillatorTc
Page 13 and 14: CC25005 Pin ConfigurationSIGNDDGUAR
Page 15 and 16: CC25006 Circuit DescriptionRADIO CO
Page 17 and 18: CC2500Component Value ManufacturerC
Page 19 and 20: CC2500Figure 6: SmartRF ® Studio u
Page 21: CC250010.1 Chip Status ByteWhen the
Page 25 and 26: CC2500MDMCFG4.MDMCFG4.CHANBW_ECHANB
Page 27 and 28: CC2500Figure 10: Data whitening in
Page 29 and 30: CC250015.3 Packet Filtering in Rece
Page 31 and 32: CC2500Phase shifts are performed wi
Page 33 and 34: CC2500Carrier Sense (CS) can be use
Page 35 and 36: CC25001) Storing codeddata2) Transm
Page 37 and 38: CC2500If the XOSC is forced on, the
Page 39 and 40: CC2500The programmable conditions a
Page 41 and 42: CC2500fcarrier=f2CHANSPC _ E−( FR
Page 43 and 44: CC2500Output power,typical, +25°C,
Page 45 and 46: CC25003530252015Selectivity [dB]105
Page 47 and 48: CC2500GDOx_CFG[5:0]] Description0 (
Page 49 and 50: CC250030.2 Frequency Hopping and Mu
Page 51 and 52: CC250031 Configuration RegistersThe
Page 53 and 54: CC2500Address Register Description
Page 55 and 56: CC250031.1 Configuration Register D
Page 57 and 58: CC25000x07: PKTCTRL1 - Packet autom
Page 59 and 60: CC25000x0B: FSCTRL1 - Frequency syn
Page 61 and 62: CC25000x12: MDMCFG2 - Modem configu
Page 63 and 64: CC25000x15: DEVIATN - Modem deviati
Page 65 and 66: CC25000x17: MCSM1 - Main Radio Cont
Page 67 and 68: CC25000x19: FOCCFG - Frequency Offs
Page 69 and 70: CC25000x1B: AGCCTRL2 - AGC controlB
Page 71 and 72: CC25000x1D: AGCCTRL0 - AGC controlB
Page 73 and 74:
CC25000x22: FREND0 - Front end TX c
Page 75 and 76:
CC25000x2C: TEST2 - Various test se
Page 77 and 78:
CC25000x36 (0xF6): WORTIME1 - High
Page 79 and 80:
CC250032.1 Recommended PCB layout f
Page 81 and 82:
CC250034.2 Product Status Definitio
Page 83 and 84:
CC2500AsiaPhone International +886-
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Single-Chip Low Cost Low Power RF-Transceiver (Rev. A)

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