Single-Chip Low Cost Low Power RF-Transceiver (Rev. A)

CC25000x16: MCSM2 – Main Radio Control State Machine configurationBit Field Name Reset R/W Description7:5 Reserved R0 Reserved4 RX_TIME_RSSI 0 R/W Direct RX termination based on RSSI measurement (carriersense).3 RX_TIME_QUAL 0 R/W When the RX_TIME timer expires the chip stays in RX mode ifsync word is found when RX_TIME_QUAL=0, or either syncword is found or PQT is set when RX_TIME_QUAL=1.2:0 RX_TIME[2:0] 7 (111) R/W Timeout for sync word search in RX. The timeout is relative tothe programmed EVENT0 timeout, which means that the dutycycle can be set in wake-on-radio (WOR) mode.The RX timeout in µs is given by EVENT0·C(RX_TIME, WOR_RES), where C is given by the table below (XOSC =26 MHz):RX_TIME[2:0] WOR_RES = 0 WOR_RES = 1 WOR_RES = 2 WOR_RES = 30 (000) 3.6058 18.0288 32.4519 46.87501 (001) 1.8029 9.0144 16.2260 23.43752 (010) 0.9014 4.5072 8.1130 11.71883 (011) 0.4507 2.2536 4.0565 5.85944 (100) 0.2254 1.1268 2.0282 2.92975 (101) 0.1127 0.5634 1.0141 1.46486 (110) 0.0563 0.2817 0.5071 0.73247 (111) Until end of packetAs an example, EVENT0 = 34666, WOR_RES = 0 and RX_TIME = 6 corresponds to 1.96 ms RX timeout, 1 spolling interval and 0.195% duty cycle. Note that WOR_RES should be 0 or 1 when using WOR.The duty cycle is approximated by:RX_TIME[2:0] WOR_RES = 0 WOR_RES = 10 (000) 12.50% 1.95%1 (001) 6.250% 9765 ppm2 (010) 3.125% 4883 ppm3 (011) 1.563% 2441 ppm4 (100) 0.781% NA5 (101) 0.391% NA6 (110) 0.195% NA7 (111) Until end of packetNote that the RC oscillator must be enabled in order to use setting 0-6, because the timeout counts RC oscillatorperiods. WOR mode does not need to be enabled.The timeout counter resolution is limited: With RX_TIME=0, the timeout count is given by the 13 MSBs of EVENT0,decreasing to the 7 MSBs of EVENT0 with RX_TIME=6.PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 64 of 83