Single-Chip Low Cost Low Power RF-Transceiver (Rev. A)

CC250015.3 Packet Filtering in Receive ModeCC2500 supports three different packet-filteringcriteria: address filtering, maximum lengthfiltering and CRC filtering.15.3.1 Address FilteringSetting PKTCTRL1.ADR_CHK to any othervalue than zero enables the packet addressfilter. The packet handler engine will comparethe destination address byte in the packet withthe programmed node address in the ADDRregister and the 0x00 broadcast address whenPKTCTRL1.ADR_CHK=10 or both 0x00 and0xFF broadcast addresses whenPKTCTRL1.ADR_CHK=11. If the receivedaddress matches a valid address, the packet isreceived and written into the RX FIFO. If theaddress match fails, the packet is discardedand receive mode restarted (regardless of theMCSM1.RXOFF_MODE setting).If the received address matches a validaddress when the packet length is set toinfinite and address filtering is enabled, 0xFFwill be written into the RX FIFO followed by theaddress byte and then the payload data.15.3.2 Maximum Length FilteringIn the variable packet length mode thePKTLEN.PACKET_LENGTH register value isused to set the maximum allowed packetlength. If the received length byte has a largervalue than this, the packet is discarded andreceive mode restarted (regardless of theMCSM1.RXOFF_MODE setting).15.3.3 CRC FilteringThe filtering of a packet when CRC check failsis enabled with PKTCTRL1.CRC_AUTOFLUSH.The CRC auto flush function will flush theentire RX FIFO if the CRC check fails. Afterauto flushing the RX FIFO, the next statedepends on the MCSM1.RXOFF_MODE setting.PKTCTRL0.CC2400_EN must be 0 (default)for the CRC auto flush function to workcorrectly.When using the auto flush function, themaximum packet length is 63 bytes in variablepacket length mode and 64 bytes in fixedpacket length mode. Note that the maximumallowed packet length is reduced by two byteswhen PKTCTRL1.APPEND_STATUS isenabled, to make room in the RX FIFO for thetwo status bytes appended at the end of thepacket. Since the entire RX FIFO is flushedwhen the CRC check fails, the previouslyreceived packet must be read out of the FIFObefore receiving the current packet. The MCUmust not read from the current packet until theCRC has been checked as OK.15.4 CRC CheckThere are two different CRC implementations.PKTCTRL0.CC2400_EN selects between the2 options. The CRC check is different for the 2options. Refer also to the CC2500 Errata Note.15.4.1 PKTCTRL0.CC2400_EN = 0If PKTCTRL0.CC2400_EN =0 it is possible toread back the CRC status in 2 different ways:1) Set PKTCTRL1.APPEND_STATUS=1 andread the CRC_OK flag in the MSB of thesecond byte appended to the RX FIFO afterthe packet data. This requires double bufferingof the packet, i.e. the entire packet content ofthe RX FIFO must be completely read outbefore it is possible to check whether the CRCindication is OK or not.2) To avoid reading the entire RX FIFO,another solution is to use thePKTCTRL1.CRC_AUTOFLUSH feature. If thisfeature is enabled, the entire RX FIFO will beflushed if the CRC check fails. IfGDOx_CFG=0x06 the GDOx pin will beasserted when a sync word is found. TheGDOx pin will be de-asserted at the end of thepacket. When the latter occurs the MCUshould read the number of bytes in the RXFIFO from the RXBYTES.NUM_RXBYTESstatus register. If RXBYTES.NUM_RXBYTES=0the CRC check failed and the FIFO is flushed.If RXBYTES.NUM_RXBYTES>0 the CRC checkwas OK and data can be read out of the FIFO.15.4.2 PKTCTRL0.CC2400_EN = 1If PKTCTRL0.CC2400_EN = 1 the CRC can bechecked as outlined in 1) in Section 15.4.1 aswell as by reading the CRC_OK flag availablein the PKTSTATUS[7] register, in the LQI[7]status register or from one of the GDO pins ifGDOx_CFG is 0x07 or 0x15.The PKTCTRL1.CRC_AUTOFLUSH or datawhitening cannot be used whenPKTCTRL0.CC2400_EN = 1.15.5 Packet Handling in Transmit ModeThe payload that is to be transmitted must bewritten into the TX FIFO. The first byte writtenmust be the length byte when variable packetPRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 29 of 83