Single-Chip Low Cost Low Power RF-Transceiver (Rev. A)

CC2500The programmable conditions are:• MCSM2.RX_TIME_QUAL=0: Continuereceive if sync word has been found• MCSM2.RX_TIME_QUAL=1: Continuereceive if sync word has been found orpreamble quality is above threshold (PQT)If the system can expect the transmission tohave started when enabling the receiver, theMCSM2.RX_TIME_RSSI function can be used.The radio controller will then terminate RX ifthe first valid carrier sense sample indicatesno carrier (RSSI below threshold). See Section17.4 on page 32 for details on Carrier Sense.For OOK modulation, lack of carrier sense isonly considered valid after eight symbolperiods. Thus, the MCSM2.RX_TIME_RSSIfunction can be used in OOK mode when thedistance between “1” symbols is 8 or less.If RX terminates due to no carrier sense whenthe MCSM2.RX_TIME_RSSI function is used,or if no sync word was found when using theMCSM2.RX_TIME timeout function, the chipwill always go back to IDLE if WOR is disabledand back to SLEEP if WOR is enabled.Otherwise, the MCSM1.RXOFF_MODE settingdetermines the state to go to when RX ends.Note that in wake-on-radio (WOR) mode, theWOR state is cleared in the latter case. Thismeans that the chip will not automatically goback to SLEEP again but to IDLE, even if e.g.the address field in the packet did not match. Itis therefore recommended to always wake upthe microcontroller on sync word detectionwhen using WOR mode. This can be done byselecting output signal 6 (see Table 33 onpage 47) on one of the programmable GDOoutput pins, and programming themicrocontroller to wake up on an edgetriggeredinterrupt from this GDO pin.20 Data FIFOThe CC2500 contains two 64 byte FIFOs, onefor received data and one for data to betransmitted. The SPI interface is used to readfrom the RX FIFO and write to the TX FIFO.Section 10.5 contains details on the SPI FIFOaccess. The FIFO controller will detectoverflow in the RX FIFO and underflow in theTX FIFO.When writing to the TX FIFO it is theresponsibility of the MCU to avoid TX FIFOoverflow. A TX FIFO overflow will result in anerror in the TX FIFO content.Likewise, when reading the RX FIFO the MCUmust avoid reading the RX FIFO past itsempty value, since an RX FIFO underflow willresult in an error in the data read out of the RXFIFO.The chip status byte that is available on the SOpin while transferring the SPI address containsthe fill grade of the RX FIFO if the address is aread operation and the fill grade of the TXFIFO if the address is a write operation.Section 10.1on page 21 contains more detailson this.The number of bytes in the RX FIFO and TXFIFO can also be read from the statusregisters RXBYTES.NUM_RXBYTES andTXBYTES.NUM_TXBYTES respectively. If areceived data byte is written to the RX FIFO atthe exact same time as the last byte in the RXFIFO is read over the SPI interface, the RXFIFO pointer is not properly updated and thelast read byte is duplicated.For packet lengths less than 64 bytes it isrecommended to wait until the completepacket has been received before reading it outof the RX FIFO.If the packet length is larger than 64 bytes theMCU must determine how many bytes can beread from the RX FIFO(RXBYTES.NUM_RXBYTES-1) and thefollowing software routine can be used:1. Read RXBYTES.NUM_RXBYTESrepeatedly at a rate guaranteed to be atleast twice that of which RF bytes arereceived until the same value is returnedtwice; store value in n.2. If n < # of bytes remaining in packet, readn-1 bytes from the RX FIFO.3. Repeat steps 1 and 2 until n = # of bytesremaining in the packet.4. Read the remaining bytes from the RXFIFO.PRELIMINARY Data Sheet (Rev.1.2) SWRS040A Page 39 of 83