European Journal of Scientific Research - EuroJournals

Effect of Scaling on the Performance of the 4-Bit CPL Subtractor Circuit 240
MOSFET are scaled down, both the voltage level and the gate-oxide thickness must also be reduced.
Since the electron thermal voltage, (kT/q) is a constant at room temperature, the ratio between the
operating voltage and the thermal voltage inevitably shrinks. This leads to higher source to-drain
leakage currents stemming from the thermal diffusion of electrons. At the same time, the gate oxide
has been scaled to a thickness of only a few atomic layers, where quantum-mechanical tunneling gives
rise to a sharp increase in gate leakage currents. The effects of these fundamental factors on CMOS
scaling are quantified [3].
According to Mead and Conway [4], any dimension in the layout design can be expressed in
terms of λ, called λ-design rule. According to the capability of silicon industry or to meet the
specification of the circuit being designed, a value may be allocated to λ, prior to manufacture. If the
CMOS scaling is given continuously it will yield miniaturization of the transistor. Smaller the
transistors, faster in action, consumes less power, lower cost and more transistors can be packed on a
chip and cost effective. Aggressive scaling of CPL devices in each technology generation has resulted
in higher integration density and performance [2, 7]. The 4 bit subtractor circuit is analyses using
device scaling technology. The scaling down of feature size generally leads to improved performance
and it is, therefore important to understand the effect of scaling. The parameter is scaled for the VLSI
fabrication technology is still in the process of evolution that is leading to smaller line widths, smaller
feature size and higher package density on a chip. Generally, subtractor circuit used as signal
propagation in the ALU which is transferring the signal without losses and only some researchers [5, 6]
has given their attention on the subtractor circuit. In this paper, we have designed a 4 bit CPL
subtractor with the help of multiplexing control input technique and studied the effect of constant field
scaling on the overall circuit performance. We have first chosen the feature size and then decided the
scaling whereas others have chosen the reverse manner. The 4 bit subtractor circuit layout is generated
with the help of Microwind 3 VLSI CAD tools and device parameters are analyzed using BSIM model.
II. Cmos Scaling Theory
Advances in silicon ULSI technology has been historically made by scaling of the device dimensions.
According to scaling theory, both lateral dimensions (i.e., lithographic feature sizes) and vertical
dimensions (e.g., junction depths) should be reduced to increase the package density of devices while
avoiding deleterious short-channel effects. The International Technology Roadmap for Semiconductors
(ITRS) [6] provides a consensus scenario of how device parameters will scale for technology
generation ranging from today’s 130-nm technology to devices as small as 22 nm in the year 2016. The
technology node parameter also called the technology generation represented the minimum
lithographic image size in earlier generations of the Roadmap, now it refers to the DRAM half-pitch.
This projected progress is even more remarkable when one notes that, for leading-edge microprocessor
chips, the physical gate length is only 60% of the node parameter, and the effective channel length
could be as little as half of the physical gate length. Thus, the Roadmap envisions devices having
effective channel lengths well under 10 nm within the next 15 years. Furthermore, the recent historical
rate of progress has been even faster than that predicted by the roadmaps or Moore’s Law [7]. Each
successive version of the ITRS Roadmap from 1994 to 2001 has been more aggressive than the
previous one: New technologies nodes have been introduced more rapidly than expected.
The overall 4 bit subtractor circuit is analyzed in terms of total power dissipation, Delay and
area by using simulation technique and scaled analysis (after scaled down) by using constant field
model. The scaled down layout is simulated by Microwind 3 and analyzed using BSIM. Scaling
depends on application, since different applications can tolerate different amounts of static leakage
power. So that, there is no single end to scaling, but rather there are different optimum ends to scaling
for different applications [7]. High power and high-performance circuits can accept much higher static
leakage dissipation than portable battery-powered devices. The smaller chip also gives smaller die size
increased yield and increased performance. The process of shrinking all geometrical dimensions and