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Effect of Scaling on the Performance of the 4-Bit CPL Subtractor Circuit 244 size (width and length of the channel situated at the intersection of the polysilicon gate and the diffusion) has a strong influence on the current. The safe way to design the circuit is to create a MOS device from the MOS generator palette. The programmable parameters are the MOS width, length, the number of gates in parallel and the type of devices (n-channel or p-channel). By default metal interconnects and contacts are added to the drain and source of the MOS. Some times if there is no interconnection of our design, we may add a supplementary metal 1 interconnect on the top of metal 1 for drain and source. V. Simulation Results and Discussion A subtractor can be constructed using the full adder blocks. This is done using a carry save adder approach. A carry save adder computes the sum of the least significant bit first, and then allows any carries to propagate to the next full adder. The sum of the first two bits is the least significant bit of the answer. The carry save subtractor operates in a similar manner, however the two’s compliment of the second input must be taken. This is done by inverting the second input and setting the carry in is logically ‘1’ on the first full subtractor. The case used to simulate the carry save subtractor involves pushing all inputs from high to low. If the inputs are all high, the difference is zero thus the output would be all low. If the circuit is pushed from all high to all low, there will be a borrow across every full subtractor. The 4-bit subtractor circuit uses 308 transistors. In this paper we have analyzed our circuit by two different approaches. Approach I: In this approach we have designed the circuit by using transistor (NMOS/PMOS) of different feature size like 120nm, 90nm, 70nm and 50nm. Then the designed circuits were simulated with help of Microwind 3 VLSI CAD tools in terms of power dissipation, delay and area. The simulated results are given in table 2. From the results, It is clear that as we are going for lower dimension transistor, the circuit performance, in terms of power dissipation and delay is improving and also area occupying by circuit on as the chip is lower. Approach II: First we designed the circuit for 150nm transistor feature size and then applying the scaling theory as given in table 1 to scale down the circuit for 120nm, 90nm, 70nm and 50nm. In this approach we are recalculating the dimension of each transistor (NMOS/PMOS) and then generating the layout of the scaled circuit by Microwind 3 CAD tool, according to resize configuration. The scaled 4 bit subtractor circuit is again simulated with Microwind 3 in terms power dissipation, propagation delay and area. As we are scaling our 4 bit subtractor circuit, power dissipation falls drastically and there is linear decrease in propagation delay. Comparison between two approaches shows that power dissipation is reduced in between 5% to 64% whereas the circuit becomes faster after scaled down. The maximum reported improvement in propagation delay of circuit after scaling is about 94% and minimum percent improvement is 65%. Therefore we can say that the tremendous speed gain is achieved after applying the scaling device theory to our 4 bit subtractor circuit. Overall area is also reduced by around 6 % to 12 % after scaling. The 4 bit subtractor circuit is gives constant power dissipation for increasing load capacitance. The load capacitance (CL) versus total power dissipation of the 4 bit subtractor circuit is shown in Fig.3. The Load capacitance (CL) is increased the power dissipation approximately constant for given VDD. According to layout parameter analysis, our circuit power dissipation is high before scaled the circuit elements. After applying scaling theory on the elements, the total power dissipation is reduced according to their dimensions, which is clearly indicating in the Fig. 3. Gate delay is proportional to output capacitance (and driving resistance) [12]. Gate delay is approximately proportional to fan-out.
245 C. Senthilpari, Ajay Kumar Singh and K. Diwakar Figure 3: Capacitance versus total Power dissipation Figure 4: Temperature Versus Maximum IDD current Our designed adder cell based subtractor circuit is analyzed for Drain current effect for various temperatures. The temperature analysis made by using BSIM advanced layout design tools for various temperatures. The temperature versus maximum IDD current graph is plotted, which is shown in Fig. 4, with help of standard feature size CMOS 120nm, CMOS 90nm, CMOS 70nm and CMOS 50nm and
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