European Journal of Scientific Research - EuroJournals

Effect of Scaling on the Performance of the 4-Bit CPL Subtractor Circuit 242
Figure 1: Block diagram of 4-bit Subtractor
The input A and complement B is fed into adder circuit, which is performing A-B. The
subtractor circuit is simulated by the Microwind 3 CAD tool and the scaling parameters are measured
by the BSIM MOS model, which is used to the accurate simulation results of submicron technology.
BSIM is an industry standard for deep-submicron device simulation. A simplified version of this model
is supported by the Microwind 3, and recommended to ultra–deep submicron technology simulation
[11]. The generated layout of the 4 bit subtractor circuit is simulated using by different feature size
such as: 120nm, 90nm, 70nm and 50nm respectively. First, the scaling device parameter calculated
theoretically using standard formulae and then the scaling device parameter verified using simulated
results of the 4 bit subtractor circuit [6]. A binary full subtractor circuit is includes an exclusive OR
gate operating upon minuend and subtrahend binary input signals. The difference output from the
circuit is the borrow input signal or its inverse depending upon the output state of the exclusive OR
gate. The borrow output of the circuit comprises either the borrow input or the subtrahend input, as
determined by the output of the exclusive OR gate and by an operation (difference) specifying input
signal. Our 4 bit subtractor circuit is designed by using CPL full adder technique. Actually our circuit
is performing in the manner of (A+ (-B)) method. The full adder circuit is designed using by
multiplexing control input technique adder cell. This technique has two stages like as; differential node
stage and swing restoration node stage which is shown in Fig.2. In this Fig.2, the input A, __
A , B and __
B
fed as an input to the pass transistor and form a multiplexing control inputs. According to stage I
(differential node) operation; we will get a result A⊕B of sum mode. This node is indicated as
differential node D in Fig.2. The differential node is the output of the A⊕B and input of the restoration
unit. In our subtractor design, the differential node A⊕B, and Ci are fed through the multiplexing
control input and form a XOR circuit for difference and XNOR for its complement. A logic circuit
combines a plurality of pass-transistor logic trees and a multiple-input logic gate for receiving logic
signals from the respective pass-transistor logic trees (differential node), and can express a complex
logical operation while decreasing the number of stages in pass-transistor logic trees and improving
operation speed. This node is called as a swing restoration node of the pass gate adder circuit. At this
node we will get the output expression Ai ⊕ Bi ⊕ Ci in sum node and complement of Ai ⊕ Bi ⊕ Ci in
sum complement node respectively. We can derive the other non-clocked pass gates depends upon
connecting component after the restoration node. Similarly, we can derive the barrow and its
complement.