European Journal of Scientific Research - EuroJournals

Effect of Scaling on the Performance of the 4-Bit CPL Subtractor Circuit 246
scaled down feature sizes. The maximum IDD is used to find out the transistor operation points.
According to Donald A. Neaman et.al [13], when temperature increased, the current will be decreased.
Any motion of free carriers in a semiconductor leads to a current. This motion can be caused by an
electric field due to an externally applied voltage, since the carriers are charged particles. This carrier
transport mechanism is due to the thermal energy and the associated random motion of the carriers. We
will refer to this transport mechanism as carrier diffusion. The total drain current in a semiconductor
equals the sum of the drift and the diffusion current. As one applies an electric field to a
semiconductor, the electrostatic force causes the carriers to first accelerate and then reach a constant
average velocity (v), due to collisions with impurities and lattice vibrations. The ratio of the velocity to
the applied field is called the mobility. The velocity saturates at high electric fields reaching the
saturation velocity. Additional scattering occurs when carriers flow at the surface of a semiconductor,
resulting in a lower mobility due to surface or interface scattering mechanisms. Diffusion of carriers is
obtained by creating a carrier density gradient. Such gradient can be obtained by varying the doping
density in a semiconductor or by applying a thermal gradient. Both carrier transport mechanisms are
related since the same particles and scattering mechanisms are involved. This leads to a relationship
between the mobility and the diffusion constant called the Einstein relation. According to Fig. 4, our 4
bit Multiplexing control input technique adder based subtractor circuit is giving low current compared
other existing circuits. So, our designed 4 bit subtractor circuits are used in low power and high speed
mobile circuits, which will give withstand long hour’s battery life.
We have compared the gate capacitance value and power dissipation of our scaled 4 bit
subtractor circuit with David Duarte et.al [14] reported results for microprocessor system. Fig 5 shows
the comparison result for gate capacitance and it s observed that the gate capacitance value decrease in
our circuit than David Duarte et.al [14]. The maximum percentage improvement of 98.30 is observed
when the circuit is scaled to 50nm. The average improvement is around 50%.
Table 2: The 4 bit subtractor circuit
Feature
size
Simulation result (Before)
Power (µW) delay Area µm
Scaling result (after applying scaling
technique)
% improvement
2 Power (µW) delay (ps) Area µm 2 Power delay Area
120nm 0.608 0.41ns 2664 0.29 28 2414 52.3 93.17 9.3
90nm 0.276 71ps 1845 0.10 25 1680 63.76 64.78 8.94
70nm 4.56 71ps 1770 4.32 18 1568 5.263 74.64 11.412
50nm 0.121 52ps 924 0.077 15 869 36.36 71.15 5.95
Figure 5: Comparison graph