TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out Functions P0 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P0.15 A10 D7 B8 C7 A11 A12 D8 B9 A13 B10 A14 C9 C10 D10 A15 B11 I/O I/O I I/O I I I/O I I I/O I I/O O I/O O I/O O I/O O I/O I/O I/O I O I O <strong>TC1765</strong> Port 0 6) Port 0 is a 16-bit bi-directional general purpose I/O port that is also used as input/output for ASC0, SSC0, CAN, GPTU, ADC0, ADC1, and the DMA Controller. GPT0 GPTU I/O line 0 / AD0EXTIN0 ADC0 external trigger input 0 GPT1 GPTU I/O line 1 AD0EXTIN1 ADC0 external trigger input 1 DMREQ0A DMA request input 0A GPT2 GPTU I/O line 2 AD1EXTIN0 ADC1 external trigger input 0 DMREQ1A DMA request input 1A GPT3 GPTU I/O line 3 AD1EXTIN1 ADC1 external trigger input 1 GPT4 GPTU I/O line 4 / AD0EMUX0 ADC0 external multiplexer control 0 GPT5 GPTU I/O line 5 AD0EMUX1 ADC0 external multiplexer control 1 GPT6 GPTU I/O line 6 AD0EMUX2 ADC0 external multiplexer control 2 RXD0 ASC0 receiver input/output TXD0 ASC0 transmitter output SCLK0 SSC0 clock input/output MRST0 SSC0 master receive input / SSC0 slave transmit output MTSR0 SSC0 master transmit output / SSC0 slave receive input RXDCAN0 CAN receiver input 0 TXDCAN0 CAN transmitter output 0 RXDCAN1 CAN receiver input 1 TXDCAN1 CAN transmitter output 1 Data Sheet 10 V1.2, 2002-12
Preliminary Table 1 Pin Definitions and Functions (cont’d) Symbol Pin In Out Functions P1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8 P1.9 P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 P2 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 N18 R16 R15 M17 N16 P15 M18 L18 P16 U16 M16 L16 K17 K18 L15 K16 J18 T15 N15 J17 H18 J16 T16 M15 J15 H16 G18 H15 G15 G17 G16 F18 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O <strong>TC1765</strong> Port 1 6) Port 1 is a 16-bit bidirectional general purpose I/O port which also serves as input or output for the GPTA. IN0 / OUT0 line of GPTA IN1 / OUT1 line of GPTA IN2 / OUT2 line of GPTA IN3 / OUT3 line of GPTA IN4 / OUT4 line of GPTA IN5 / OUT5 line of GPTA IN6 / OUT6 line of GPTA IN7 / OUT7 line of GPTA IN8 / OUT8 line of GPTA IN09 / OUT9 line of GPTA IN10 / OUT10 line of GPTA IN11 / OUT11 line of GPTA IN12 / OUT12 line of GPTA IN13 / OUT13 line of GPTA IN14 / OUT14 line of GPTA IN15 / OUT15 line of GPTA Port 2 6) Port 2 is a 16-bit bidirectional general purpose I/O port which also serves as input or output for the GPTA. IN16 / OUT16 line of GPTA IN17 / OUT17 line of GPTA IN18 / OUT18 line of GPTA IN19 / OUT19 line of GPTA IN20 / OUT20 line of GPTA IN21 / OUT21 line of GPTA IN22 / OUT22 line of GPTA IN23 / OUT23 line of GPTA IN24 / OUT24 line of GPTA IN25 / OUT25 line of GPTA IN26 / OUT26 line of GPTA IN27 / OUT27 line of GPTA IN28 / OUT28 line of GPTA IN29 / OUT29 line of GPTA IN30 / OUT30 line of GPTA IN31 / OUT31 line of GPTA Data Sheet 11 V1.2, 2002-12
Page 1 and 2: TC1765 Microcontrollers Data Sheet,
Page 3 and 4: TC1765 Microcontrollers Data Sheet,
Page 5 and 6: Preliminary 32-Bit Single-Chip Micr
Page 7 and 8: Preliminary Block Diagram PMU (Prog
Page 9 and 10: Preliminary Pin Configuration A B C
Page 11 and 12: Preliminary Table 1 Pin Definitions
Page 13: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66:
Preliminary Input/Output DC-Charact
Page 67 and 68:
Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70:
Preliminary AD Converter Characteri
Page 71 and 72:
Preliminary Figure 22 Equivalent Ci
Page 73 and 74:
Preliminary Power Supply Current TA
Page 75 and 76:
Preliminary Testing Waveforms TA =
Page 77 and 78:
Preliminary ECOUT and CPUCLK Timing
Page 79 and 80:
Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82:
Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84:
Preliminary WAIT Timing (FPI Bus to
Page 85 and 86:
Preliminary TC1765 Trace Port Timin
Page 87 and 88:
Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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