TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon
TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon
TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon
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Preliminary<br />
Ports Power Supply<br />
<strong>TC1765</strong><br />
The <strong>TC1765</strong>’s port power supply concept is shown in Figure 19. The External Bus Unit<br />
(EBU) I/O lines are in the core and EBU V DD power supply group for 2.5 V nominal<br />
operating voltage. The general purpose input/outputs (GPIOs) provide 3.3 to 5 V nominal<br />
voltage input/output acceptance and drive characteristics.<br />
V DD<br />
(2.5 V)<br />
EBU I/O Lines<br />
(Pa<strong>ds</strong>)<br />
&<br />
Schmitt Trigger<br />
Port Logic<br />
Figure 19 Ports Power Supply Concept<br />
V DDP<br />
(3.3 - 5 V)<br />
Ports 0 to 5<br />
(Pa<strong>ds</strong>)<br />
&<br />
Schmitt Trigger<br />
MCA05226<br />
Power-up Sequence<br />
During Power-up the reset pin PORST has to be held active until both power supply<br />
voltages have reached at least their minimum values.<br />
During the Power-up time (rising of the supply voltages from 0 to their regular operating<br />
values) it has to be ensured, that the difference between VDDP and VDD never drops<br />
below -0.5 V.<br />
Power Loss<br />
If VDDP is dropping below VDD, external circuitry in the power supply has to ensure, that<br />
VDD is also limited to the same level.<br />
If VDDI is dropping below the operating range, VDDP may stay active.<br />
Powering Down<br />
During powering down (falling of the supply voltages from their regular operating values<br />
to zero), it has to be ensured, that the difference between VDDP and VDD never drops<br />
below -0.5 V.<br />
Data Sheet 54 V1.2, 2002-12<br />
V SS