TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary TC1765 The bit timings for both CAN nodes are derived from the peripheral clock (f CAN) and are programmable up to a data rate of 1 Mbit/s. A pair of receive and transmit pins connect each CAN node to a bus transceiver. Features: CAN functionality conforms to CAN specification V2.0 B active. Dedicated control registers are provided for each CAN node. A data transfer rate up to 1 Mbit/s is supported. Flexible and powerful message transfer control and error handling capabilities are implemented. Full-CAN functionality: 32 message objects can be individually – Assigned to one of the two CAN nodes – Configured as transmit or receive object – Participate in a 2, 4, 8, 16 or 32 message buffer with FIFO algorithm – Set up to handle frames with 11-bit or 29-bit identifiers – Provided with programmable acceptance mask register for filtering – Monitored via a frame counter – Configured to Remote Monitoring Mode Up to eight individually programmable interrupt nodes can be used. CAN Analyzer Mode for bus monitoring is implemented. Data Sheet 24 V1.2, 2002-12
Preliminary Timer Units The TC1765 includes two timer units: – General Purpose Timer Unit (GPTU) – General Purpose Timer Array (GPTA) General Purpose Timer Unit Figure 8 shows a global view of the General Purpose Timer Unit (GPTU) module. Clock Control Address Decoder Interrupt Control Figure 8 General Block Diagram of the GPTU Interface TC1765 The GPTU consists of three 32-bit timers designed to solve such application tasks as event timing, event counting, and event recording. The GPTU communicates with the external world via eight inputs and eight outputs located at Port 0. The I/O has three timers (T0, T1, and T2) can operate independently from each other, or can be combined. General Features: f GPTU SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7 GPTU Module (Kernel) IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 Port Control P0.1 / GPT1 MCB05052 All timers are 32-bit precision timers with a maximum input frequency of f GPTU . Events generated in T0 or T1 can be used to trigger actions in T2. Timer overflow or underflow in T2 can be used to clock either T0 or T1. T0 and T1 can be concatenated to form one 64-bit timer. Data Sheet 25 V1.2, 2002-12 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 P0.0 / GPT0 P0.2 / GPT2 P0.3 / GPT3 P0.4 / GPT4 P0.5 / GPT5 P0.6 / GPT6 Not Connected
Page 1 and 2: TC1765 Microcontrollers Data Sheet,
Page 3 and 4: TC1765 Microcontrollers Data Sheet,
Page 5 and 6: Preliminary 32-Bit Single-Chip Micr
Page 7 and 8: Preliminary Block Diagram PMU (Prog
Page 9 and 10: Preliminary Pin Configuration A B C
Page 11 and 12: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27: Preliminary TwinCAN Interface Figur
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80:
Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82:
Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84:
Preliminary WAIT Timing (FPI Bus to
Page 85 and 86:
Preliminary TC1765 Trace Port Timin
Page 87 and 88:
Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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