TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary Input/Output DC-Characteristics (cont’d) VSS = 0 V; TA = -40 °C to +125 °C; Parameter1) Symbol Limit Values Unit Test Conditions min. max. Pin capacitance 10) (Digital I/O) C IO CC – 10 pF f = 1 MHz T A = 25 °C Class C Pins (V DDOSC = 2.30 to 2.75 V), see Page 68 TC1765 1) All Class A pins of the TC1765 are equipped with Low-Noise output drivers, which significantly improve the device’s EMI performance. These Low-Noise drivers deliver their maximum current only until the respective target output level is reached. After that the output current is reduced. This results in an increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current, which is specified in column “Test Conditions”, is delivered in any case. 2) This specification is not valid for outputs of GPIO lines, which are switched to open drain mode. In open drain mode the output will float and the voltage results from the external circuitry. 3) Output drivers in high current mode. 4) Condition for output driver in dynamic current mode & low current mode – guaranteed by design characterization. 5) Input characteristics can be switched between TTL and CMOS via register Px_PICON except for dedicated pins which have CMOS input characteristics. 6) The maximum current can be drawn while the respective signal line remains inactive. 7) The two pull-up/pull-down current test conditions for VOUT cover the curves as shown in Figure 20 and Figure 21. All pull-up/pull-down currents are given as absolute values. 8) The minimum current must be drawn in order to drive the respective signal line active. 9) In case of Class B pins V DDx = V DD . In case of Class A pins V DDx = V DDP . 10) Guaranteed by design characterization. 11) The test condition for Class A pins is: VDDP = 4.5 to 5.25 V; for Class B pins: V DD = 2.3 to 2.75 V; 12) The max. peak-short-circuit current resp. max. peak-back-drive current is limited by max. 20 mA and the peak period equivalent of 10 mA constant-short-circuit current resp. 10 mA constant-back-drive current. The integral of I SCBDpeak over the peak period is thus limited to 10 mA (provided: I SCBDpeak ≤ 20 mA). 13) To be defined for Class B pads. 14) Short-circuit or back-drive conditions during operation occur if the voltage on the respective pin exceeds the specified operating range (i.e. V SCBD > V DDP + 0.5 V or V SCBD < V SS - 0.5 V) or a short circuit condition occurs on the respective pin. The absolute sum of input I SCBD and I OV currents on all port pins must not exceed 100 mA at any time. The supply voltage (V DDP and V SS) must remain within the specified limits. Under shortcircuit conditions the corresponding pin is not ready for use. In case of Class B pins V DDx = V DD. In case of Class A pins V DDx = V DDP. Data Sheet 62 V1.2, 2002-12
Preliminary Pull-Up/Pull-Down Characteristics 700 µA I 600 500 400 300 200 100 0 0 Best Case Nominal Worst Case Pull-up 1 2 3 4 5 V V 6 700 µA I 600 Figure 20 Pull-Up/Pull-Down Characteristics of Class A Pins MCD05139 TC1765 Data Sheet 63 V1.2, 2002-12 500 400 300 200 100 0 0 Pull-down Best Case Nominal Worst Case 1 2 3 4 5 V V 6
Page 1 and 2:
TC1765 Microcontrollers Data Sheet,
Page 3 and 4:
TC1765 Microcontrollers Data Sheet,
Page 5 and 6:
Preliminary 32-Bit Single-Chip Micr
Page 7 and 8:
Preliminary Block Diagram PMU (Prog
Page 9 and 10:
Preliminary Pin Configuration A B C
Page 11 and 12:
Preliminary Table 1 Pin Definitions
Page 13 and 14:
Preliminary Table 1 Pin Definitions
Page 15 and 16: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65: Preliminary Input/Output DC-Charact
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84: Preliminary WAIT Timing (FPI Bus to
Page 85 and 86: Preliminary TC1765 Trace Port Timin
Page 87 and 88: Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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