TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary <strong>TC1765</strong> and reception of data are double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial clock signal. Features: Master and slave mode operation – Full-duplex or half-duplex operation Flexible data format – Programmable number of data bits: 2-bit to 16 bit – Programmable shift direction: LSB or MSB shift first – Programmable clock polarity: idle low or high state for the shift clock – Programmable clock/data phase: data shift with leading or trailing edge of the shift clock Baud rate generation from 20 Mbit/s to 305.18 Bit/s (@ 40 MHz module clock) Interrupt generation – On a transmitter empty condition – On a receiver full condition – On an error condition (receive, phase, baud rate, transmit error) Three-pin interface – Flexible SSC pin configuration 4-stage receive FIFO (RXFIFO) and 4-stage transmit FIFO (TXFIFO) – Independent control of RXFIFO and TXFIFO – 2 to 16 bit FIFO data width – Programmable receive/transmit interrupt trigger level – Receive and transmit FIFO filling level indication – Overrun error generation – Underflow error generation Data Sheet 22 V1.2, 2002-12
Preliminary TwinCAN Interface Figure 7 shows a global view of the functional blocks of the TwinCAN module. Clock Control Address Decoder Interrupt Control f CAN SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7 TwinCAN Module Kernel Interrupt Control Bitstream Processor Message Buffers Timing Control Error Handling Control TXDC0 RXDC0 TXDC1 RXDC1 Port Control Figure 7 General Block Diagram of the TwinCAN Module <strong>TC1765</strong> P0.13 / TXDCAN0 P0.12 / RXDCAN0 P0.15 / TXDCAN1 P0.14 / RXDCAN1 MCB05059 The TwinCAN module has four I/O lines located at Port 0. The TwinCAN module is further supplied by a clock control, interrupt control, address decoding, and port control logic. The TwinCAN module contains two Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames are handled in accordance to CAN specification V2.0 part B (active). Each of the two Full-CAN nodes can receive and transmit standard frames with 11-bit identifiers as well as with extended frames with 29-bit identifiers. Both CAN nodes share the TwinCAN module’s resources to optimize the CAN bus traffic handling and to minimize the CPU load. The flexible combination of Full-CAN functionality and the FIFO architecture reduces the efforts to fulfill the real-time requirements of complex embedded control applications. Improved CAN bus monitoring functionality as well as the increased number of message objects permit precise and convenient CAN bus traffic handling. Depending on the application, each of the thirty-two message objects can be individually assigned to one of the two CAN nodes. Gateway functionality allows automatic data exchange between two separate CAN bus systems, which decreases CPU load and improves the real time behavior of the entire system. Data Sheet 23 V1.2, 2002-12
Page 1 and 2: TC1765 Microcontrollers Data Sheet,
Page 3 and 4: TC1765 Microcontrollers Data Sheet,
Page 5 and 6: Preliminary 32-Bit Single-Chip Micr
Page 7 and 8: Preliminary Block Diagram PMU (Prog
Page 9 and 10: Preliminary Pin Configuration A B C
Page 11 and 12: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25: Preliminary TC1765 High-Speed Synch
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78:
Preliminary ECOUT and CPUCLK Timing
Page 79 and 80:
Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82:
Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84:
Preliminary WAIT Timing (FPI Bus to
Page 85 and 86:
Preliminary TC1765 Trace Port Timin
Page 87 and 88:
Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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