TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

Preliminary
SSC Master Mode Timing
VSS = 0 V; VDDP = 4.5 to 5.25 V; TA = -40 °C to +125 °C; CL = 50 pF;
Figure 35 SSC Master Mode Timing
TC1765
Parameter Symbol Limit Values Unit
min. max.
SCLK / MTSR low/high from ECOUT
1) t60 CC – 7 ns
MRST setup to SLCK rising/falling edge t61 SR 18 2)
– ns
MRST hold from SLCK rising/falling edge t62 SR 10 2)
– ns
1) This parameter is valid for high current mode output driver characteristic and normal timing edge characteristic
(POCON.PECx = 0 and POCON.PDCx = 0) of the corresponding SSC output lines.
2) Guaranteed by design characterization.
ECOUT
SCLK
MTSR
MRST
t 60
t ECOUT
t 60
State n-1 State n
State n+1
t 61
MCT05234
Data Sheet 82 V1.2, 2002-12
t 62
Data Valid
Note: The timing diagram assumes the highest possible baudrate operation.
(f SSC = f ECOUT , SSCx_CLC.RMC = 1, SSCx_BR.BR_VALUE = 0000 H )
t 60