TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary ECOUT A[23:0] CODE 1) SVM ADV CSx RD RD/WR D[31:0] BC[3:0] t 10 t 10 t 10 Data Valid t 10 t 11 t 11 t 10 Figure 31 EBU Demultiplexed Write Timing t 11 t 11 Address Valid 1) CODE remains at high level during a demultiplexed write cycle <strong>TC1765</strong> MCT05230 Data Sheet 78 V1.2, 2002-12 t 11 t 11 t 10 t 15
Preliminary WAIT Timing (FPI Bus to External Memory) VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF; Figure 32 WAIT Timing (from FPI Bus to external Memory) <strong>TC1765</strong> Parameter Symbol Limit Values Unit min. max. WAIT setup to ECOUT t50 SR 14 1) – ns WAIT hold from ECOUT t51 SR 14 1) – ns WAIT setup to ECOUT t52 SR 11 – ns WAIT hold from ECOUT t53 SR 2 – ns 1) Guaranteed by design characterization. Synchronous Mode ECOUT WAIT Asynchronous Mode ECOUT WAIT t 50 t 52 MCT05231 Data Sheet 79 V1.2, 2002-12 t 51 t 53 t 50 t 52 t 51 t 53
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TC1765 Microcontrollers Data Sheet,
Page 3 and 4:
TC1765 Microcontrollers Data Sheet,
Page 5 and 6:
Preliminary 32-Bit Single-Chip Micr
Page 7 and 8:
Preliminary Block Diagram PMU (Prog
Page 9 and 10:
Preliminary Pin Configuration A B C
Page 11 and 12:
Preliminary Table 1 Pin Definitions
Page 13 and 14:
Page 15 and 16:
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Page 19 and 20:
Page 21 and 22:
Page 23 and 24:
Preliminary Serial Interfaces The T
Page 25 and 26:
Preliminary TC1765 High-Speed Synch
Page 27 and 28:
Preliminary TwinCAN Interface Figur
Page 29 and 30:
Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81: Preliminary ECOUT ECIN A[23:0] CODE
Page 85 and 86: Preliminary TC1765 Trace Port Timin
Page 87 and 88: Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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