TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

More documents

Recommendations

Info

Preliminary DMA Request Bus 1 2 2 2 2 6 6 Service Requestors GPTU GPTA SSC0 SSC1 ASC0 ASC1 CAN DMA ADC0 ADC1 BCU Debug Unit 8 SRNs 54 SRNs Figure 14 Block Diagram of the TC1765 Interrupt System 8 54 3 3 4 4 8 8 4 4 1 1 Service Request Nodes 3 SRNs 3 SRNs 4 SRNs 4 SRNs 8 SRNs 8 SRNs 4 SRNs 4 SRNs 1 SRN 1 SRN TC1765 MCB04993 Data Sheet 46 V1.2, 2002-12 8 54 3 3 4 4 8 8 4 4 1 1 Interrupt Arbitration Bus 4 4 SRNs Interrupt Control Unit ICU Int. Req. PIPN 4 Software Interrupts CPU Int. Ack. CCPN
Preliminary TC1765 Boot Options The TC1765 booting schemes provides a number of different boot options for the start of code execution. Table 4 shows the boot options available in the TC1765. Table 4 TC1765 Boot Selections OCDSE BRKIN CFG[2:0] Type of Boot Boot Source PC Start Value 1 1 000BStart from Boot ROM Entry Point 1 Boot ROM BFFF FFFCH 001 B 010 B 011 B 100 B 101 B 110B 111B 0 1 100B or 101B all other combinations Start from Boot ROM Entry Point 2 Start from Boot ROM Entry Point 3 Start from Boot ROM Entry Point 4 External memory as master directly PMU - EBU External Memory External memory via PMU - FPI Bus - EBU Reserved; don’t use these combinations. Go to halt with EBU enabled as master Go to halt with EBU disabled 0 0 – Go to external emulator space 1 0 – Tri-state chip (deep sleep) – – A000 0000 H – BE00 0000 H – – Data Sheet 47 V1.2, 2002-12
Page 1 and 2: TC1765 Microcontrollers Data Sheet,
Page 3 and 4: TC1765 Microcontrollers Data Sheet,
Page 5 and 6: Preliminary 32-Bit Single-Chip Micr
Page 7 and 8: Preliminary Block Diagram PMU (Prog
Page 9 and 10: Preliminary Pin Configuration A B C
Page 11 and 12: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49: Preliminary TC1765 Interrupt System
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84: Preliminary WAIT Timing (FPI Bus to
Page 85 and 86: Preliminary TC1765 Trace Port Timin
Page 87 and 88: Preliminary Package Outlines P-LBGA

TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?