TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary f ADC A/D Converter Module Peripheral Clock Divider (1:1) to (1:8) f DIV Figure 23 ADC Clock Circuit TC1765 Note: The frequency of f ADC is the system clock frequency (f SYS) divided by the value of bit field ADCx_CLC.RMC. Oscillator Pins (Class C Pins) TA = -40 °C to +125 °C; VDDOSC = 2.30 to 2.75 V; VSSOSC = 0 V; Parameter Symbol Limit values Unit Test Conditions min. max. Input low voltage at XTAL1 VILX SR -0.5 0.3 × VDDOSC V – Input high voltage at XTAL1 VIHX RR 0.7 × VDDOSC VDDOSC +0.5 V – Input current at XTAL1 IIX1 CC – ±20 µA 0 V < VIN < VDDOSC Input leakage current XTAL1 1) IOZ CC – ±200 nA 0 V < VIN < VDDOSC 1) Only applicable in deep sleep mode. Programmable Clock Divider (1:1) to (1:128) MCA04657 Data Sheet 68 V1.2, 2002-12 f BC 4:1 3:1 f ANA Programmable Counter CON.PCD CON.CTC CON.CPS CHCONn.STC Arbiter (1:20) f TIMER Control Unit (Timer) Control/Status Logic Interrupt Logic External Trigger Logic External Multiplexer Logic Request Generation Logic Sample Time t S
Preliminary Power Supply Current TA = -40 °C to +125 °C; TC1765 Parameter Symbol Limit Values Unit Test Conditions min. typ. 1) max. Active mode supply current IDD CC – – 200 mA 2)3) PORST = VIL 1) Parameters in this column are tested at 25 °C, 40 MHz system clock (if applicable) and nominal VDD voltages. 2) These parameters are tested at VDDmax and 40 MHz system clock (bypass mode) with all outputs disconnected and all inputs at V IL or V IH . 3) These power supply currents are defined as the sum of all currents at the VDD power supply lines: V DD + V DDP + V DDRAM + V DDSBRAM + V DDOSC + V DDM + V DDA0 + V DDA1 – 260 290 mA Sum of I DDS 4)3) – 7 10 mA I DD at V DDP 4) – 201 – mA I DD at V DD (Core and EBU) 4) – 31 – mA 4) IDD at VDDRAM – 21 4) 120 5) mA IDD at VDDSBRAM – 0.1 – mA 4) IDD at VDDAx Idle mode supply current I ID CC – 123 – mA PORST = V IH 2)6)7) Sleep mode supply current I SL CC – 50 – mA PORST = V IH 2)7) Deep sleep mode supply current Stand-by pin power supply current 4) These power consumption characteristics are measured while running a typical application pattern. The power consumption of modules can increase or decrease using other application programs. The PLL is inactive during this measurement. 5) This parameter has been evaluated at design characterization using an atypical test pattern that makes extensive usage of the DMU memory. 6) All peripherals are enabled and in idle state. 7) Guaranteed by design characterization. 8) This is the sum of all 2.5 V power supply currents. 9) This is the sum of all 5 V power supply currents. 10) TC1765 in deep sleep mode. 11) All other VDD pins are at 0 V; T J = 150 °C; V DDSBRAM = 2.0 V. I DS CC – 5 900 µA PORST = V IH 8) – 1 4.4 mA 9) PORST = VIH ISB CC – 1 250 µA 10) IDD at VDDSBRAM – 1 200 µA Data Sheet 69 V1.2, 2002-12 11)
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TC1765 Microcontrollers Data Sheet,
Page 3 and 4:
TC1765 Microcontrollers Data Sheet,
Page 5 and 6:
Preliminary 32-Bit Single-Chip Micr
Page 7 and 8:
Preliminary Block Diagram PMU (Prog
Page 9 and 10:
Preliminary Pin Configuration A B C
Page 11 and 12:
Preliminary Table 1 Pin Definitions
Page 13 and 14:
Page 15 and 16:
Page 17 and 18:
Page 19 and 20:
Page 21 and 22: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71: Preliminary Figure 22 Equivalent Ci
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84: Preliminary WAIT Timing (FPI Bus to
Page 85 and 86: Preliminary TC1765 Trace Port Timin
Page 87 and 88: Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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