TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary TC1765 PLL Parameters Note: All PLL characteristics defined on this and the next page are guaranteed by design characterization. V SS = 0 V; V DD = 2.30 to 2.75 V; T A = -40 °C to +125 °C; Parameter Symbol Limit Values Unit min. max. Accumulated jitter DN see Figure 29 – VCO frequency range fVCO 150 200 MHz PLL base frequency fPLLBASE 40 130 MHz PLL lock-in time tL – 200 µs Phase Locked Loop Operation When PLL operation is enabled and configured (see Figure 16 and Page 51), the PLL clock fVCO (and with it the system clock fSYS ) is constantly adjusted to the selected frequency. The relation between fVCO and fSYS is defined by: fVCO =K× fSYS. The PLL causes a jitter of fSYS and CPUCLK/ECOUT, which is directly derived from fSYS and which has its frequency. The following two formulas define the (absolute) approximate maximum value of jitter DN in ns dependent on the K-factor, the system clock frequency fSYS in MHz, and the number P of consecutive fSYS periods. for P < 23.5 K for P > 23.5 K D N [ns] = ± D N [ns] = ± 3.9 f SYS [MHz] × P + 1.2 With rising number P of clock cycles the maximum jitter increases linearly up to a value of P that is defined by the K-factor of the PLL. Beyond this value of P the maximum accumulated jitter remains at a constant value. Further, a lower system clock frequency fSYS results in a higher maximum jitter. Figure 29 gives an example for typical jitter curves with K =4@40MHz, K = 6 @33 MHz, and K = 8@20/25 MHz. 91.7 f SYS [MHz] × K + 1.2 Data Sheet 74 V1.2, 2002-12 [1] [2]
Preliminary ±2.0 ns D N ±1.8 ±1.6 ±1.4 ±1.2 ±1.0 0 D N P K f SYS = 20 MHz (K = 8) f SYS = 25 MHz (K = 8) f SYS = 33 MHz (K = 6) f SYS = 40 MHz (K = 4) 1 2 3 4 5 6 = M ax. jitter = Number of consecutive f SYS periods = K-divider of PLL MCD05141_mod TC1765 Figure 29 Approximated Maximum Accumulated PLL Jitter for Typical System Clock Frequencies f SYS Note: For safe clock generation and PLL operation the definitions and restrictions as defined at pages 50, 51, and 72 must be regarded. Data Sheet 75 V1.2, 2002-12 P 7
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TC1765 Microcontrollers Data Sheet,
Page 3 and 4:
TC1765 Microcontrollers Data Sheet,
Page 5 and 6:
Preliminary 32-Bit Single-Chip Micr
Page 7 and 8:
Preliminary Block Diagram PMU (Prog
Page 9 and 10:
Preliminary Pin Configuration A B C
Page 11 and 12:
Preliminary Table 1 Pin Definitions
Page 13 and 14:
Page 15 and 16:
Page 17 and 18:
Page 19 and 20:
Page 21 and 22:
Page 23 and 24:
Preliminary Serial Interfaces The T
Page 25 and 26:
Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77: Preliminary ECOUT and CPUCLK Timing
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84: Preliminary WAIT Timing (FPI Bus to
Page 85 and 86: Preliminary TC1765 Trace Port Timin
Page 87 and 88: Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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