TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

Preliminary
TC1765
External Bus Unit
The External Bus Unit (EBU) of the TC1765 is the interface between external memories
and peripheral units and the internal memories and peripheral units. The basic structure
of the EBU is shown in Figure 11.
TriCore
CPU
PMU
with on-chip
Progam Memory
DMU
with on-chip
Data Memory
FPI Bus
Burst Mode
Instruction
Fetches
Figure 11 EBU Structure and Interfaces
To Peripheral
Units and DMA
MCA04983
The EBU consists of two parts and is used for the following two operations:
FBU (FPI Bus Unit):
– Communication with external memories or peripheral units via the FPI Bus
– Non-burst instruction fetches
BIFU (Burst Instruction Fetch Unit):
– Instruction fetches from the PMU to external Burst Flash program memories with
16-bit and 32-bit data width
The EBU controls all transactions required for these two operations and in particular
handles the arbitration between these two tasks.
The types of external devices/Bus modes controlled by the FBU are:
– INTEL style peripherals (separate RD and WR signals)
– MOTOROLA style peripherals (OE and R/W)
– ROMs, EPROMs
– Static RAMs
– Peripherals with demultiplexed A/D bus
– Burst Mode Flash Memories
– 8-, 16- and 32-bit data bus width
Data Sheet 39 V1.2, 2002-12
BIFU
EBU
FBU
10
5
Control
Lines
Chip Select
Lines
A[23:0]
D[31:0]
ECIN
ECOUT