TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary EBU Burst Mode Timing VSS = 0 V, VDD = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF; Figure 33 Burst Mode Timing (Instruction Read) TC1765 Parameter Symbol Limit Values Unit min. max. Output delay from ECIN t30 CC 2 14 ns Data setup to ECIN t31 SR 4 1) – ns Data hold from ECIN t32 SR 1 1) – ns 1) Guaranteed by design characterization. ECIN A[23:2] ADV CS0 CODE RD BAA D[31:0] t 30 t 30 t 30 Note: WAIT must be 1 during a Burst Mode Read Cycle. t 30 t 30 Address Valid Data Sheet 80 V1.2, 2002-12 t 30 t 31 Valid t 30 t 32 t 31 t 32 Valid t 30 t 30 MCT05232
Preliminary TC1765 Trace Port Timing (TC1765T only) This timing is applicable for TP[15:0] when CPU or DMA trace mode is enabled (SCU_CON.ETEN = 1). VSS = 0 V; VDD = 2.30 to 2.75 V; TA = -40 °C to +125 °C; CL = 50 pF; Parameter Symbol Limit Values Unit min. max. TP[15:0] and BRKOUT high/low from CPUCLK t55 CC 0 8 ns CPUCLK TP[15:0] BRKOUT Figure 34 Trace Port Timing MCT05233 Data Sheet 81 V1.2, 2002-12 t 55 Old State New State
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TC1765 Microcontrollers Data Sheet,
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TC1765 Microcontrollers Data Sheet,
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Preliminary 32-Bit Single-Chip Micr
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Preliminary Block Diagram PMU (Prog
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Preliminary Pin Configuration A B C
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Preliminary Table 1 Pin Definitions
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Preliminary Serial Interfaces The T
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Preliminary TC1765 High-Speed Synch
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Preliminary TwinCAN Interface Figur
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Preliminary Timer Units The TC1765
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Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83: Preliminary WAIT Timing (FPI Bus to
Page 87 and 88: Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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