TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary TC1765 On-Chip Memories The memory system of the TC1765 provides the following memories: Program Memory Unit (PMU) with – 8 Kbytes Boot ROM (BROM) – 16 Kbytes Code Scratch-Pad RAM (SPRAM) – 1 Kbyte Instruction Cache (ICACHE) Data Memory Unit (DMU) with – 32 Kbytes Data Memory (SRAM) – Can be used for standby operation during power-down states using a separate power supply Data Sheet 32 V1.2, 2002-12
Preliminary TC1765 Address Map Table 2 defines the segment oriented address blocks of the TC1765 with its address range, size, and PMU/DMU access view. Table 3 shows the block address map of segment 15 which includes the on-chip peripheral units. Table 2 TC1765 Block Address Map Segment Address Range 0 - 7 0000 0000H - 7FFF FFFFH 8 8000 0000H - 8FFF FFFFH 9 9000 0000H - 9FFF FFFFH 10 A000 0000H - AFFF FFFFH 11 B000 0000 H - BDFF FFFF H BE00 0000H - BEFF FFFFH BF00 0000H - BFFF DFFFH BFFF E000H - BFFF FFFFH 12 C000 0000H - C000 3FFFH C000 4000H - C7FF FEFFH C7FF FF00H - C7FF FFFFH C800 0000H - CFFF FFFFH Size Description DMU Acc. 2 GB Reserved – – 256 MB Reserved via FPI 256 MB Reserved DMU local 256 MB External Memory Space via FPI 224 MB External Memory Space mappable into Segment 10 PMU Acc. 1) PMU local via FPI via EBU or FPI via EBU or FPI 16 MB External Emulator Space via via FPI -16 MB Reserved FPI 8 KB Boot ROM 4 Kbytes general purpose 4 Kbytes factory test support 16 KB Local Code Scratch-Pad RAM (SPRAM) – Reserved 256 B PMU Control Registers – Reserved PMU local Data Sheet 33 V1.2, 2002-12 via FPI PMU local cached non-cached
Page 1 and 2: TC1765 Microcontrollers Data Sheet,
Page 3 and 4: TC1765 Microcontrollers Data Sheet,
Page 5 and 6: Preliminary 32-Bit Single-Chip Micr
Page 7 and 8: Preliminary Block Diagram PMU (Prog
Page 9 and 10: Preliminary Pin Configuration A B C
Page 11 and 12: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35: Preliminary Clock Control Address D
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84: Preliminary WAIT Timing (FPI Bus to
Page 85 and 86: Preliminary TC1765 Trace Port Timin
Page 87 and 88:
Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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