TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary I 250 µA 200 150 100 50 0 0 Best Case Nominal Worst Case Pull-up 0.5 1 1.5 2 2.5 V 3 V Figure 21 Pull-Up/Pull-Down Characteristics of Class B Pins MCD05140 <strong>TC1765</strong> Note: The pull-up/pull-down characteristics as shown in Figure 20 and Figure 21 are guaranteed by design characterization. Data Sheet 64 V1.2, 2002-12 I 250 µA 200 150 100 50 0 0 Pull-down Best Case Nominal Worst Case 0.5 1 1.5 2 2.5 V 3 V
Preliminary AD Converter Characteristics VSS = 0 V; TA = -40 °C to +125 °C; Parameter Symbol Limit Values Unit Test min. typ. max. Conditions Analog supply voltages VDDAx SR 2.25 2.5 2.75 V 1) VDDM SR 4.5 5 5.25 V – Analog ground voltage VSSAx SR -0.1 – 0.1 V 1) Analog reference voltage Analog reference ground Analog input voltage range V AREFx SR 4 – V DDM + 0.05 V VAGNDx SR VSSAx - 0.05 VAIN SR VAGNDx – VAREFx V 1) <strong>TC1765</strong> Data Sheet 65 V1.2, 2002-12 1)2) – V SSAx + 0.05 V 1)3) Internal ADC clock f ANA 0.5 – 5 MHz – Power-up calibration time t PUC CC – – 3328 × (3 + CON.CPS) × t BC Sample time t S CC (3 + CON.CPS) × (CHCONn.STC + 2) × t BC µs – 6 × tBC – – µs Conversion time tC CC tS + (30 + CON.CPS × 4) × tBC + 2 × tDIV µs for 8-bit conv. 4) tS + (36 + CON.CPS × 4) × tBC + 2 × tDIV µs for 10-bit conv. 4) ts + (42 + CON.CPS × 4) × tBC + 2 × tDIV µs for 12-bit conv. 4) Total unadjusted error TUE 5) CC – – ±1 LSB for 8-bit conv. – – ±2 LSB for 10-bit conv. – – ±6 LSB for 12-bit conv. Overload current6) I 7) AOV1 CC -2 – +5 mA – -2 0 mA kA =1.0 × 10 -3 Overload coupling factor 9) 0 +5 mA k A =1.0 × 10 -4 I 8) AOV2 CC -4 – +10 mA – -4 0 mA kA =1.0 × 10-3 0 +10 mA k A =1.0 × 10 -4 k A CC – – 1.0 × 10 -3 – see I AOV1 and I AOV2 1.0 × 10 -4 – µs 4)
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TC1765 Microcontrollers Data Sheet,
Page 3 and 4:
TC1765 Microcontrollers Data Sheet,
Page 5 and 6:
Preliminary 32-Bit Single-Chip Micr
Page 7 and 8:
Preliminary Block Diagram PMU (Prog
Page 9 and 10:
Preliminary Pin Configuration A B C
Page 11 and 12:
Preliminary Table 1 Pin Definitions
Page 13 and 14:
Page 15 and 16:
Page 17 and 18: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67: Preliminary Pull-Up/Pull-Down Chara
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84: Preliminary WAIT Timing (FPI Bus to
Page 85 and 86: Preliminary TC1765 Trace Port Timin
Page 87 and 88: Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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