TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

Preliminary
Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin In
Out
Functions
P5
P5.0
P5.1
P5.2
P5.3
P5.4
TP
TP.0
TP.1
TP.2
TP.3
TP.4
TP.5
TP.6
TP.7
TP.8
TP.9
TP.10
TP.11
TP.12
TP.13
TP.14
TP.15
TRST 7)
TCK 7)
TDI 8)
D12
B13
B14
C11
A16
G7
G8
H7
H8
L7
L8
M7
M8
M11
M12
L11
L12
H11
H12
G11
G12
I/O
I/O
I
O
I
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
TC1765
Port 56) Port 5 is a 5-bit bidirectional general purpose I/O port which
also serves as input or output for ASC1 and SSC1.
RXD1 ASC1 receiver input/output
DMREQ0C DMA request input 0C
TXD1 ASC1 transmitter output
DMREQ1C DMA request input 1C
SCLK1 SSC1 clock input/output
MRST1 SSC1 master receive input /
SSC1 slave transmit output
MTSR1 SSC1 master transmit output /
SSC1 slave receive input
OCDS-2 Trace Port 3)
TP is the OCDS Level 2 Trace Port. The Trace port is only
available in the TC1765T. The TP outputs are tristated during
reset and deep sleep mode.
Trace output 0
Trace output 1
Trace output 2
Trace output 3
Trace output 4
Trace output 5
Trace output 6
Trace output 7
Trace output 8
Trace output 9
Trace output 10
Trace output 11
Trace output 12
Trace output 13
Trace output 14
Trace output 15
R14 I JTAG Module Reset/Enable Input
A low level at this pin resets and disables the JTAG module.
A high level enables the JTAG module.
T13 I JTAG Module Clock Input
T14 I JTAG Module Serial Data Input
Data Sheet 13 V1.2, 2002-12