TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary AD Converter Characteristics (cont’d) V SS = 0 V; T A = -40 °C to +125 °C; Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Input leakage current at analog inputs Input leakage current at V AGND and V AREF Switched cap. at positive reference voltage input Switched cap. at negative reference voltage input Total capacitance at analog voltage input Switched cap. at analog voltage input ON resistance of the transmission gates in the analog voltage path TC1765 I OZ1 CC – – ±200 nA 0 V< V IN < V DDA 1) I OZ2 CC – – ±500 nA 0 V< V IN < V DDA 1) C AREFSW CC C AGNDSW CC – 15 20 pF Data Sheet 66 V1.2, 2002-12 10) – 15 20 pF 10) CAINTOT – 12 15 pF – CC CAINSW CC – – 10 pF 11) R AIN CC – – 0.7 kΩ – 1) Suffix x = 0 refers to ADC0 and suffix x = 1 refers to ADC1. 2) The value of VAREF is permitted to be within the range of V SSA - 0.05 V < V AREF < V DDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the V AREF is out of the specified range. 3) The value of VAGND is permitted to be within the range of V SSA - 0.05 V < V AGND < V DDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the V AGND is out of the specified range. 4) Definitions for CPS, STC, tBC and t DIV see Figure 23. 5) TUE is tested at VAREF = 5 V, V AGND = 0 V and V DDM = 4.9 V. 6) Analog overload conditions during operation occur if the voltage on the respective ADC pin exceeds the specified operating range (i.e. V AOV > V DDM + 0.5 V or V AOV < V SSM - 0.5 V) or a short circuit condition occurs on the respective ADC pin. The absolute sum of input currents on all port pins must not exceed 10 mA at any time. The supply voltage (V DD, V DDA0, V DDA1 and V SS, V SSA0, V SSA1) must remain within the specified limits. Under short-circuit conditions the corresponding pin is not ready for use. 7) Applies for one analog input pin. 8) Applies for two numeric adjacent analog input pins.
Preliminary Figure 22 Equivalent Circuitry of Analog Input TC1765 9) The overload coupling factor (kA) defines the worst case relation of an overload condition (I OV) at one pin to the resulting leakage current (I leak) into an adjacent pin: |I leak| = k A × |I OV|. Thus under overload conditions an additional error leakage voltage (V AEL) will be induced onto an adjacent analog input pin due to the resistance of the analog input source (R AIN). That means V AEL = R AIN × |I leak|. See also section 7.1.6 “Error Through Overload Conditions” in the TC1765 Peripheral Units User’s Manual for further explanations. 10) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage at once. Instead of this smaller capacitances are successively switched to the reference voltage. Alternatively, the redistributed charge could be specified. 11) The switched capacitance at the analog voltage input must be charged within the sampling time. Alternatively, the redistributed charge could be specified. V AIN = R AIN, Source C AIN, Block R AIN, On C AINTOT - C AINSW A/D Converter C AINSW MCS04879 Note: This equivalent circuitry for an analog input is also valid for the reference inputs V AREF and V AGND. Data Sheet 67 V1.2, 2002-12
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TC1765 Microcontrollers Data Sheet,
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TC1765 Microcontrollers Data Sheet,
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Preliminary 32-Bit Single-Chip Micr
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Preliminary Block Diagram PMU (Prog
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Preliminary Pin Configuration A B C
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Preliminary Table 1 Pin Definitions
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Page 19 and 20: Preliminary Table 1 Pin Definitions
Page 21 and 22: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69: Preliminary AD Converter Characteri
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84: Preliminary WAIT Timing (FPI Bus to
Page 85 and 86: Preliminary TC1765 Trace Port Timin
Page 87 and 88: Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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