TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary TC1765 The General Purpose Timer Array (GPTA) provides a set of hardware modules required for high speed digital signal processing: Filter and Prescaler Cells (FPC) support input noise filtering and prescaler operation. Phase Discrimination Logic units (PDL) decode the direction information output by a rotation tracking system. Duty Cycle Measurement Cells (DCM) provide pulse width measurement capabilities. A Digital Phase Locked Loop unit (PLL) generates a programmable number of GPTA module clock ticks during an input signal’s period. Global Timer units (GT) driven by various clock sources are implemented to operate as a time base for the associated “Global Timer Cells”. Global Timer Cells (GTC) can be programmed to capture the contents of a Global Timer on an event that occurred at an external port pin or at an internal FPC output. A GTC may be also used to control an external port pin with the result of an internal compare operation. GTCs can be logically concatenated to provide a common external port pin with a complex signal waveform. Local Timer Cells (LTC) operating in Timer, Capture, or Compare Mode may be also logically tied together to drive a common external port pin with a complex signal waveform. LTCs — enabled in Timer Mode or Capture Mode — can be clocked or triggered by – A prescaled GPTA module clock, – An FPC, PDL, DCM, PLL, or GTC output signal line, – An external port pin. Some input lines driven by processor I/O pads may be shared by a LTC and a GTC cell to trigger their programmed operation simultaneously. The following list summarizes all blocks supported: Clock Generation Unit: Filter and Prescaler Cell (FPC): – Six independent units – Three operating modes (Prescaler, Delayed Debounce Filter, Immediate Debounce Filter) – f GPTA down-scaling capability – f GPTA/2 maximum input signal frequency in Filter Mode Phase Discriminator Logic (PDL): – Two independent units – Two operating modes (2 and 3 sensor signals) – f GPTA /4 maximum input signal frequency in 2-sensor mode, f GPTA /6 maximum input signal frequency in 3-sensor mode Duty Cycle Measurement (DCM): – Four independent units – 0 - 100% margin and time-out handling Data Sheet 28 V1.2, 2002-12
Preliminary – f GPTA maximum resolution – f GPTA /2 maximum input signal frequency Digital Phase Locked Loop (PLL): – One unit – Arbitrary multiplication factor between 1 and 65535 – f GPTA maximum resolution – f GPTA/2 maximum input signal frequency Signal Generation Unit: Global Timers (GT): – Two independent units – Two operating modes (Free Running Timer and Reload Timer) – 24-bit data width – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency Global Timer Cell (GTC): – 32 independent units – Two operating modes (Capture, Compare and Capture after Compare) – 24-bit data width – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency Local Timer Cell (LTC): – 64 independent units – Three operating modes (Timer, Capture and Compare) – 16-bit data width – fGPTA maximum resolution – fGPTA/2 maximum input signal frequency Interrupt Control Unit: 111 interrupt sources generating 54 service requests I/O Sharing Unit: Interconnecting input and output lines from FPC, GTC, LTC and ports Emergency function TC1765 Data Sheet 29 V1.2, 2002-12
Page 1 and 2: TC1765 Microcontrollers Data Sheet,
Page 3 and 4: TC1765 Microcontrollers Data Sheet,
Page 5 and 6: Preliminary 32-Bit Single-Chip Micr
Page 7 and 8: Preliminary Block Diagram PMU (Prog
Page 9 and 10: Preliminary Pin Configuration A B C
Page 11 and 12: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31: Preliminary TC1765 General Purpose
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84:
Preliminary WAIT Timing (FPI Bus to
Page 85 and 86:
Preliminary TC1765 Trace Port Timin
Page 87 and 88:
Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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