TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary Package Parameters (P-LBGA-260) Parameter Symbol Limit Values Unit Notes min. max. TC1765 Power dissipation PDISS – 0.9 W – Thermal resistance RTHA – 24.8 K/W Chip to ambient Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1765. All parameters specified in the following table refer to these operating conditions, unless otherwise noticed. Parameter Symbol Limit Values Unit Notes min. max. Digital supply voltage 1) VDDP 3.0 5.25 2) V Class A pins VDD VDDOSC VDDRAM 2.3 2.75 3) V Class B and Class C pins 4) VDDSBRAM 2.25 2.75 V 4)5) Digital ground voltage VSS 0 V – TA -40 +125 °C – Ambient temperature under bias Analog supply voltages VDDA 2.25 2.75 V – VDDM 4.5 5.25 V – Analog reference voltage V AREF 4 V DDM + 0.05 Analog ground voltage V AGND V SSA - 0.05 V SSA + 0.05 Analog input voltage V AIN V AGND V AREF V – CPU clock fSYS – 40 MHz – Overload current IOV -10 10 mA 8)9)10) Short circuit current ISC -10 10 mA 5)6)11) Absolute sum of overload + short circuit currents Σ|I OV| + |I SC| Data Sheet 58 V1.2, 2002-12 V V 6) 7) – |50| mA 9) External load capacitance C L – 50 pF –
Preliminary TC1765 1) Digital supply voltages applied to the TC1765 must be static regulated voltages which allow a typical voltage swing of ±10%. 2) Voltage overshoot to 6.5 V is permissible, provided that the pulse duration is less than 100 µs and the cumulated summary of the pulses does not exceed 1 hour. 3) Voltage overshoot to 4 V is permissible, provided that the pulse duration is less than 100 µs and the cumulated summary of the pulses does not exceed 1 hour. 4) In order to minimize the danger of latch-up conditions, these 2.5 V V DD power supply pins should be kept at the same voltage level during normal operating mode. This condition is typically achieved by generating the 2.5 V power supplies from a single voltage source. The condition is also valid in normal operating mode if a separate stand-by power supply V DDSBRAM is used. 5) The minimum voltage at pin VDDSBRAM during TC1765 power down mode is 1.8 V in order to keep the contents of SBRAM valid. The core power supply V DD must be below the standby power supply V DD < V DDSBRAM + 0.3 V. 6) The value of VAREF is permitted to be within the range of V SSA - 0.05 V < V AREF < V DDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the V AREF is out of the specified range. 7) The value of VAGND is permitted to be within the range of V SSA - 0.05 V < V AGND < V DDM + 0.05 V. The value specified for the total unadjusted error (TUE) is not guaranteed while the V AGND is out of the specified range. 8) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. V OV > V DD + 0.5 V or V OV < V SS - 0.5 V). The absolute sum of input overload currents on all port pins may not exceed 50 mA. The supply voltage must remain within the specified limits. 9) Not 100% tested, guaranteed by design and characterization. 10) Applicable for analog inputs. 11) Applicable for digital inputs. Data Sheet 59 V1.2, 2002-12
Page 1 and 2:
TC1765 Microcontrollers Data Sheet,
Page 3 and 4:
TC1765 Microcontrollers Data Sheet,
Page 5 and 6:
Preliminary 32-Bit Single-Chip Micr
Page 7 and 8:
Preliminary Block Diagram PMU (Prog
Page 9 and 10:
Preliminary Pin Configuration A B C
Page 11 and 12: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61: Preliminary Absolute Maximum Rating
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84: Preliminary WAIT Timing (FPI Bus to
Page 85 and 86: Preliminary TC1765 Trace Port Timin
Page 87 and 88: Preliminary Package Outlines P-LBGA
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