TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary SSC Master Mode Timing VSS = 0 V; VDDP = 4.5 to 5.25 V; TA = -40 °C to +125 °C; CL = 50 pF; Figure 35 SSC Master Mode Timing TC1765 Parameter Symbol Limit Values Unit min. max. SCLK / MTSR low/high from ECOUT 1) t60 CC – 7 ns MRST setup to SLCK rising/falling edge t61 SR 18 2) – ns MRST hold from SLCK rising/falling edge t62 SR 10 2) – ns 1) This parameter is valid for high current mode output driver characteristic and normal timing edge characteristic (POCON.PECx = 0 and POCON.PDCx = 0) of the corresponding SSC output lines. 2) Guaranteed by design characterization. ECOUT SCLK MTSR MRST t 60 t ECOUT t 60 State n-1 State n State n+1 t 61 MCT05234 Data Sheet 82 V1.2, 2002-12 t 62 Data Valid Note: The timing diagram assumes the highest possible baudrate operation. (f SSC = f ECOUT , SSCx_CLC.RMC = 1, SSCx_BR.BR_VALUE = 0000 H ) t 60
Preliminary Package Outlines P-LBGA-260-2 Plastic Low Profile Pitch Ball Grid Array You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. SMD = Surface Mounted Device TC1765 GPA09421 Dimensions in mm Data Sheet 83 V1.2, 2002-12
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TC1765 Microcontrollers Data Sheet,
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TC1765 Microcontrollers Data Sheet,
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Preliminary 32-Bit Single-Chip Micr
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Preliminary Block Diagram PMU (Prog
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Preliminary Pin Configuration A B C
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Preliminary Table 1 Pin Definitions
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Preliminary Serial Interfaces The T
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Preliminary TC1765 High-Speed Synch
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Preliminary TwinCAN Interface Figur
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Preliminary Timer Units The TC1765
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Preliminary TC1765 General Purpose
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Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84: Preliminary WAIT Timing (FPI Bus to
Page 85: Preliminary TC1765 Trace Port Timin
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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