TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary AC Characteristics Output Rise/Fall Times Class A drivers (GPIO Ports 0 to 5): VDDP = 3.0 to 5.25 V; VSS = 0 V Class B drivers (Bus interface): VDD = 2.30 to 2.75 V; VSS = 0 V TA = -40 °C to +125 °C, unless otherwise noted; fSYS = 40 MHz Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Class A Pins Nominal output rise/ fall time 1) Maximal output rise/ fall time 1) Slow output rise/fall time 1) Class B Pins t RFAnom CC t RFAmax CC t RFAslow CC Output rise/fall time 1) t RFBmax CC 1) Measured from 10% output level to 90% output level and vice versa. <strong>TC1765</strong> – 5 – ns T A = 25 °C, C L = 50 pF, V DDP = 5.0 V Px_POCON.PDCy = 0 Px_POCON.PECy = 0 – – 12 ns C L = 50 pF Px_POCON.PDCy = 0 Px_POCON.PECy = 0 – – 55 ns C L = 100 pF Px_POCON.PDCy = 0 Px_POCON.PECy = 1 – – 4 ns for ECOUT CL = 50 pF – – 7 ns for all Class B pins except ECOUT CL = 50 pF Data Sheet 70 V1.2, 2002-12
Preliminary Testing Waveforms TA = -40 °C to +125 °C; Frequency: max. 40 MHz; Class A Pins: VDDP813 = 3.0 to 5.25 V; VSS = 0 V; V IHmin V ILmax V OHmin V OLmax Test Points Figure 24 Testing Waveforms for Class A Pins Class B and Class C Pins: V DD = 2.30 to 2.75 V; V SS = 0 V; V DDOSC = 2.30 to 2.75 V; V SSOSC = 0 V; Figure 25 Testing Waveforms for Class B and Class C Pins Figure 26 Tri-State Testing Waveforms for Class B Pins V OHmin V OLmax MCT04880 AC inputs during testing are driven with VIHmin for a logic 1 and VILmax for a logic 0. Timing measurements are made at VOHmin for a logic 1 and VOLmax for a logic 0. Input and Output Low/High max./min. voltages are defined at Page 60. V IHmin V ILmax V DD / 2 Test Points V DD / 2 MCT04881 AC inputs during testing are driven with V IHmin for a logic 1 and V ILmax for a logic 0. Timing measurements are made at V DD /2 for a logic 1 and for a logic 0. Input Low/High max./min. voltages are defined at Page 61 and Page 68. V Load + 0.1 V V OH - 0.1 V Timing Reference Points V Load - 0.1 V V OL - 0.1 V MCT05074 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded V OH/V OL level occurs (I OH/I OL = 15 mA). <strong>TC1765</strong> Data Sheet 71 V1.2, 2002-12
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TC1765 Microcontrollers Data Sheet,
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TC1765 Microcontrollers Data Sheet,
Page 5 and 6:
Preliminary 32-Bit Single-Chip Micr
Page 7 and 8:
Preliminary Block Diagram PMU (Prog
Page 9 and 10:
Preliminary Pin Configuration A B C
Page 11 and 12:
Preliminary Table 1 Pin Definitions
Page 13 and 14:
Page 15 and 16:
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Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73: Preliminary Power Supply Current TA
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84: Preliminary WAIT Timing (FPI Bus to
Page 85 and 86: Preliminary TC1765 Trace Port Timin
Page 87 and 88: Preliminary Package Outlines P-LBGA
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