TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary TC1765 DMA Controller The Direct Memory Access (DMA) Controller executes DMA transactions from a source address location to a destination address location, without intervention of the CPU. One DMA transaction is controlled by one DMA channel. Each of the two blocks in the DMA controller, block 0 and block 1 (see Figure 12), provides four DMA channels with sixteen DMA request inputs. The request assignment unit in each sub-block assigns one DMA request input to each DMA channel. The control unit includes a third request unit dedicated especially for request control through I/O pins. This unit connects two of eight request inputs with two request outputs which can be then wired externally of the DMA controller module to the request inputs of the two DMA controller blocks. Request assignment unit 2 evaluates pulses or levels by its edge detect and level select logic. Features: 8 independent DMA channels (4 per DMA block) – 4 DMA selectable request inputs per DMA channel – Fixed priority of DMA channels within a DMA block – Software and hardware DMA request generation Support of FPI Bus to FPI Bus DMA transactions Individually programmable operation modes for each DMA channel – Single mode: stops and disables DMA channel after a predefined number of DMA transfers – Continuous mode: DMA channel remains enabled after a predefined number of DMA transfers; DMA transaction can be repeated Full 32-bit addressing capability of each DMA channel – 4 Gbyte address range – Source and destination transfer individually programmable in steps from 0 to 255 bytes – Support of circular buffer addressing mode Programmable data width of a DMA transaction: 8-bit, 16-bit, or 32-bit Register set for each DMA channel – Source and destination start address register – Source and destination end address register – Channel control and status register – Offset and transfer count register Bus bandwidth allocation Flexible interrupt generation Figure 12 shows the TC1765 specific implementation details and interconnections of the DMA module. The DMA module is further supplied by a separate clock control, address decoding, interrupt control, port control logic. Data Sheet 40 V1.2, 2002-12
Preliminary Clock Control Address Decoder Interrupt Control f DMA SR0 SR1 SR6 SR7 DMA Controller DMA Channels 00-03 Control Unit DMA Channels 10-13 Sub-Block 0 Sub-Block 1 Request Assign. Unit 0 Request Assign. Unit 2 Request Assign. Unit 1 Figure 12 DMA Module Block Diagram with Interconnections TC1765 MCB04965 Data Sheet 41 V1.2, 2002-12 16 4 REQO0 REQO1 4 16 DMA Request Wiring Matrix GPTA3 (GTC30) ASC0 ASC1 SSC0 SSC1 ADC0 ADC1 GPTA3 (LTC54) P0.1 / DMREQ0A P4.1 / DMREQ0B P5.0 / DMREQ0C P0.2 / DMREQ1A P4.2 / DMREQ1B P5.1 / DMREQ1C
Page 1 and 2: TC1765 Microcontrollers Data Sheet,
Page 3 and 4: TC1765 Microcontrollers Data Sheet,
Page 5 and 6: Preliminary 32-Bit Single-Chip Micr
Page 7 and 8: Preliminary Block Diagram PMU (Prog
Page 9 and 10: Preliminary Pin Configuration A B C
Page 11 and 12: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43: Preliminary TC1765 External Bus Uni
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84: Preliminary WAIT Timing (FPI Bus to
Page 85 and 86: Preliminary TC1765 Trace Port Timin
Page 87 and 88: Preliminary Package Outlines P-LBGA

TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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