TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary TC1765 Parallel Ports The TC1765 has 77 digital input/output port lines organized into four parallel 16-bit ports (Port 0 to Port 3), one 8-bit port (Port 4), and one 5-bit port (Port 5). Additionally, 24 analog input port lines are available. The External Bus Unit (EBU) is provided with dedicated data, address, and control lines. A 16-bit Trace Port is available only in the TC1765T. The digital parallel ports Port 0 to Port 5 can be all used as general purpose I/O lines or they can perform input/output functions for the on-chip peripheral units. The on-chip External Bus Interface Unit allows to communicate with external memories, external peripherals, or external debugging devices. An overview on the port-to-peripheral unit assignment is shown in Figure 4. Note: For further details on the three pin classes of the TC1765 I/O pins see also Table 8 on Page 56): External Bus Interface Data Bus D[31:0] Address Bus A[23:0] Control Lines TP[15:0] OCDS Trace Port (TC1765T only) TC1765N TC1765T Parallel Ports AN[23:0] Figure 4 Parallel Ports of the TC1765 GPIO Alternate Functions Port 0 GPTU / ASC0 / SSC0 / CAN / ADC0 / ADC1 Port 1 Port 2 Port 3 Port 4 Port 5 GPTA GPTA GPTA GPTA / CFG ASC1 / SSC1 MCA04981 Data Sheet 18 V1.2, 2002-12
Preliminary Serial Interfaces The TC1765 includes five serial peripheral interface units: – Two Asynchronous/Synchronous Serial Interfaces (ASC0 and ASC1) – Two High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) – One TwinCAN Interface TC1765 Asynchronous/Synchronous Serial Interfaces Figure 5 shows a global view of the functional blocks of the two Asynchronous/ Synchronous Serial interfaces ASC0 and ASC1. Clock Control Address Decoder Interrupt Control To DMA Clock Control Address Decoder Interrupt Control To DMA f ASC0 EIR TBIR TIR RIR f ASC1 EIR TBIR TIR RIR ASC0 Module (Kernel) ASC1 Module (Kernel) RXD0 TXD0 RXD1 TXD1 Port 0 Control Port 5 Control Figure 5 General Block Diagram of the ASC Interfaces P0.7 / RXD0 P0.8 / TXD0 P5.0 / RXD1 P5.1 / TXD1 MCB05050 Data Sheet 19 V1.2, 2002-12
Page 1 and 2: TC1765 Microcontrollers Data Sheet,
Page 3 and 4: TC1765 Microcontrollers Data Sheet,
Page 5 and 6: Preliminary 32-Bit Single-Chip Micr
Page 7 and 8: Preliminary Block Diagram PMU (Prog
Page 9 and 10: Preliminary Pin Configuration A B C
Page 11 and 12: Preliminary Table 1 Pin Definitions
Page 21: Preliminary Table 1 Pin Definitions
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74:
Preliminary Power Supply Current TA
Page 75 and 76:
Preliminary Testing Waveforms TA =
Page 77 and 78:
Preliminary ECOUT and CPUCLK Timing
Page 79 and 80:
Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82:
Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84:
Preliminary WAIT Timing (FPI Bus to
Page 85 and 86:
Preliminary TC1765 Trace Port Timin
Page 87 and 88:
Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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