TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary TC1765 Parameter Interpretation The parameters listed on the following pages partly represent the characteristics of the TC1765 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column “Symbol”: CC (Controller Characteristics): The logic of the TC1765 will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the TC1765. Pin Classes The TC1765 has three classes of digital I/O pins: – Class A pins, which are 3.0 to 5.25 V voltage pins – Class B pins, which are 2.5 V nominal voltage pins (input tolerant for 3.3 V) – Class C pins, which are 2.5 V nominal voltage pins only Table 8 shows the assignments of all digital I/O pins to pin classes and to V DD power supply pins. Table 8 Assignments of Digital Pins to Pin Classes and Power Supply Pins Pins Pin Classes Power Supply Port 0 to Port 5, BYPASS, HDRST Class A (3.0 to 5.25 V) VDDP VSS D[31:0], A[23:0], CS[3:0], CSEMU/CSOVL, BC[3:0], RD, RD/WR, ADV, WAIT/IND, BAA, CODE, TRST, TCK, TDI, TDO, TMS, ODCSE, BRKIN, BRKOUT, NMI, PORST, ECOUT, ECIN, CPUCLK, TESTMODE, TP[15:0] Class B (nominal 2.5 V) VDD XTAL1, XTAL2 Class C (nominal 2.5 V) VDDOSC VSSOSC No pins assigned (nominal 2.5 V) VDDRAM VDDSBRAM VSS Data Sheet 56 V1.2, 2002-12
Preliminary Absolute Maximum Ratings Parameter Symbol Limit Values Unit Notes min. max. TC1765 Ambient temperature TA -40 125 °C under bias Storage temperature TA -65 150 °C – Junction temperature TJ – 150 °C under bias VDD -0.5 6.2 V see Table 8 Voltage on VDDP with respect to VSS Voltage on VDD , VDDOSC , VDDRAM and VDDSBRAM with respect to VSS Voltage on any Class A input pin with respect to VSS Voltage on any Class B input pin with respect to VSS Voltage on any Class C input pin with respect to VSS Input current on any pin during overload condition Absolute sum of all input currents during overload condition V DD -0.5 3.25 V – V IN -0.5 V DD + 0.5 V – V IN -0.5 3.7 V – V IN -0.5 V DDOSC + 0.5 V – I IN -10 10 mA – ΣI IN – |100| mA – Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (V IN > V DD or V IN < V SS ) the voltage on V DD pins with respect to ground (V SS) must not exceed the values defined by the absolute maximum ratings. Data Sheet 57 V1.2, 2002-12
Page 1 and 2:
TC1765 Microcontrollers Data Sheet,
Page 3 and 4:
TC1765 Microcontrollers Data Sheet,
Page 5 and 6:
Preliminary 32-Bit Single-Chip Micr
Page 7 and 8:
Preliminary Block Diagram PMU (Prog
Page 9 and 10: Preliminary Pin Configuration A B C
Page 11 and 12: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29 and 30: Preliminary Timer Units The TC1765
Page 31 and 32: Preliminary TC1765 General Purpose
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59: Preliminary Identification Register
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82: Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84: Preliminary WAIT Timing (FPI Bus to
Page 85 and 86: Preliminary TC1765 Trace Port Timin
Page 87 and 88: Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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