TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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Preliminary <strong>TC1765</strong> Features of T0 and T1: Each timer has a dedicated 32-bit reload register with automatic reload on overflow. Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers. Overflow signals can be selected to generate service requests, pin output signals, and T2 trigger events. Two input pins can define a count option. Features of T2: Count up or down is selectable Operating modes: – Timer – Counter – Quadrature counter (incremental/phase encoded counter interface) Options: – External start/stop, one-shot operation, timer clear on external event – Count direction control through software or an external event – Two 32-bit reload/capture registers Reload modes: – Reload on overflow or underflow – Reload on external event: positive transition, negative transition, or both transitions Capture modes: – Capture on external event: positive transition, negative transition, or both transitions – Capture and clear timer on external event: positive transition, negative transition, or both transitions Can be split into two 16-bit counter/timers Timer count, reload, capture, and trigger functions can be assigned to input pins. T0 and T1 overflow events can also be assigned to these functions. Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle output pins. T2 events are freely assignable to the service request nodes. Data Sheet 26 V1.2, 2002-12
Preliminary <strong>TC1765</strong> General Purpose Timer Array Figure 9 shows a global block diagram of the General Purpose Timer Array (GPTA). Clock Control Address Decoder Interrupt Control A/D Converter f GPTA SR00 SR01 SR52 SR53 GTC30 To DMA LTC54 PTIN00 PTIN01 PTIN10 PTIN11 GPTA Module Kernel Clock Generation Unit Filter & Prescaler Cells Duty Cycle Measurement Phase Discriminator Logic Digital Phase Locked Loop Signal Generation Unit Global Timer Cells Global Timers Local Timer Cells Interrupt Control Unit Figure 9 GPTA Module Block Diagram Port Control IO 54 IO 55 MCB05053 The GPTA module has 56 input signals and 56 output signals which are connected with 56 Port 1, Port 2, Port 3, and Port 4 pins. The General Purpose Timer Array (GPTA) provides important digital signal filtering and timer support whose combination enables autonomous and complex functionalities. This architecture allows easy implementation and easy validation of any kind of timer functions. Data Sheet 27 V1.2, 2002-12 IO Sharing Unit with Emergency Shut-Off IN0 IN1 IN54 IN55 AS0 AS1 AS54 AS55 OUT0 OUT1 OUT54 OUT55 IO0 IO1 IO 14 IO 15 IO 16 IO 17 IO 30 IO 31 IO 32 IO 33 IO 46 IO 47 IO 48 IO 49 P1.0 P1.1 P1.14 P1.15 P2.0 P2.1 P2.14 P2.15 P3.0 P3.1 P3.14 P3.15 P4.0 P4.1 P4.6 P4.7
Page 1 and 2: TC1765 Microcontrollers Data Sheet,
Page 3 and 4: TC1765 Microcontrollers Data Sheet,
Page 5 and 6: Preliminary 32-Bit Single-Chip Micr
Page 7 and 8: Preliminary Block Diagram PMU (Prog
Page 9 and 10: Preliminary Pin Configuration A B C
Page 11 and 12: Preliminary Table 1 Pin Definitions
Page 23 and 24: Preliminary Serial Interfaces The T
Page 25 and 26: Preliminary TC1765 High-Speed Synch
Page 27 and 28: Preliminary TwinCAN Interface Figur
Page 29: Preliminary Timer Units The TC1765
Page 33 and 34: Preliminary - f GPTA maximum resolu
Page 35 and 36: Preliminary Clock Control Address D
Page 37 and 38: Preliminary TC1765 Address Map Tabl
Page 39 and 40: Preliminary Table 3 Block Address M
Page 41 and 42: Preliminary TC1765 Memory Protectio
Page 43 and 44: Preliminary TC1765 External Bus Uni
Page 45 and 46: Preliminary Clock Control Address D
Page 47 and 48: Preliminary TC1765 Watchdog Timer T
Page 49 and 50: Preliminary TC1765 Interrupt System
Page 51 and 52: Preliminary TC1765 Boot Options The
Page 53 and 54: Preliminary TC1765 On-Chip Debug Su
Page 55 and 56: Preliminary TC1765 PLL Operation Th
Page 57 and 58: Preliminary TC1765 Power Supply Fig
Page 59 and 60: Preliminary Identification Register
Page 61 and 62: Preliminary Absolute Maximum Rating
Page 63 and 64: Preliminary TC1765 1) Digital suppl
Page 65 and 66: Preliminary Input/Output DC-Charact
Page 67 and 68: Preliminary Pull-Up/Pull-Down Chara
Page 69 and 70: Preliminary AD Converter Characteri
Page 71 and 72: Preliminary Figure 22 Equivalent Ci
Page 73 and 74: Preliminary Power Supply Current TA
Page 75 and 76: Preliminary Testing Waveforms TA =
Page 77 and 78: Preliminary ECOUT and CPUCLK Timing
Page 79 and 80: Preliminary ±2.0 ns D N ±1.8 ±1.
Page 81 and 82:
Preliminary ECOUT ECIN A[23:0] CODE
Page 83 and 84:
Preliminary WAIT Timing (FPI Bus to
Page 85 and 86:
Preliminary TC1765 Trace Port Timin
Page 87 and 88:
Preliminary Package Outlines P-LBGA
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TC1765_ds_v12 (TC1765_ds_v12_1202.pdf) - Infineon

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