MC9S12VR-Family - Data Sheet - Freescale Semiconductor

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S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) 4.3.2.8 S12CPMU_UHV RTI Control Register (CPMURTI) This register selects the time-out period for the Real Time Interrupt. The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else the RTI counter halts in Stop Mode. 0x003B R W Read: Anytime Write: Anytime 7 6 5 4 3 2 1 0 RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 Reset 0 0 0 0 0 0 0 0 Figure 4-11. S12CPMU_UHV RTI Control Register (CPMURTI) NOTE A write to this register starts the RTI time-out period. A change of the RTIOSCSEL bit (writing a different value or loosing UPOSC status) re-starts the RTI time-out period. Table 4-9. CPMURTI Field Descriptions Field Description 7 RTDEC 6–4 RTR[6:4] 3–0 RTR[3:0] Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values. 0 Binary based divider value. See Table 4-10 1 Decimal based divider value. See Table 4-11 Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI.See Table 4-10 and Table 4-11. Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to provide additional granularity.Table 4-10 and Table 4-11 show all possible divide values selectable by the CPMURTI register. MC9S12VR Family Reference Manual, Rev. 2.8 138 Freescale Semiconductor
RTR[3:0] 0000 (÷1) 000 (OFF) OFF 1 Table 4-10. RTI Frequency Divide Rates for RTDEC = 0 001 (2 10 ) 2 10 0001 (÷2) OFF 2x2 10 0010 (÷3) OFF 3x2 10 0011 (÷4) OFF 4x2 10 0100 (÷5) OFF 5x2 10 0101 (÷6) OFF 6x2 10 0110 (÷7) OFF 7x2 10 0111 (÷8) OFF 8x2 10 010 (2 11 ) 2 11 2x2 11 3x2 11 4x2 11 5x2 11 6x2 11 7x2 11 8x2 11 MC9S12VR Family Reference Manual, Rev. 2.8 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV) RTR[6:4] = 1000 (÷9) OFF 9x2 10 9x2 11 9x2 12 9x2 13 9x2 14 9x2 15 9x2 16 1001 (÷10) OFF 10x2 10 10x2 11 10x2 12 10x2 13 10x2 14 10x2 15 10x2 16 1010 (÷11) OFF 11x2 10 11x2 11 11x2 12 11x2 13 11x2 14 11x2 15 11x2 16 1011 (÷12) OFF 12x2 10 12x2 11 12x2 12 12x2 13 12x2 14 12x2 15 12x2 16 1100 (÷13) OFF 13x2 10 13x2 11 13x2 12 13x2 13 13x2 14 13x2 15 13x2 16 1101 (÷14) OFF 14x2 10 14x2 11 14x2 12 14x2 13 14x2 14 14x2 15 14x2 16 1110 (÷15) OFF 15x2 10 15x2 11 15x2 12 15x2 13 15x2 14 15x2 15 15x2 16 1111 (÷16) OFF 16x2 10 16x2 11 16x2 12 16x2 13 16x2 14 16x2 15 16x2 16 1 Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. Freescale Semiconductor 139 011 (2 12 ) 2 12 2x2 12 3x2 12 4x2 12 5x2 12 6x2 12 7x2 12 8x2 12 100 (2 13 ) 2 13 2x2 13 3x2 13 4x2 13 5x2 13 6x2 13 7x2 13 8x2 13 101 (2 14 ) 2 14 2x2 14 3x2 14 4x2 14 5x2 14 6x2 14 7x2 14 8x2 14 110 (2 15 ) 2 15 2x2 15 3x2 15 4x2 15 5x2 15 6x2 15 7x2 15 8x2 15 111 (2 16 ) 2 16 2x2 16 3x2 16 4x2 16 5x2 16 6x2 16 7x2 16 8x2 16
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MC9S12VR-Family Reference Manual S1
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Chapter 1 Device Overview MC9S12VR-
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2.3.34 Port L Analog Access Registe
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5.2 External Signal Description . .
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Chapter 9 Pulse-Width Modulator (S1
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12.4.6 Gated Time Accumulation Mode
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16.1.2 Modes of Operation . . . . .
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Appendix H LSDRV Electrical Specifi
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1.3 Chip-Level Features Feature MC9
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1.4.4 Main External Oscillator (XOS
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• Programmable polarity for trans
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1.5 Block Diagram PE0 PE1 VSUP VSS
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Address Module NOTE Reserved regist
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1.6.1 Part ID Assignments MC9S12VR
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1.7.2.7 PS[5:0] — Port S I/O Sign
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1.7.2.21 IOC[3:0] Signals MC9S12VR
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1.8.1 Pinout 48-pin LQFP LGND LIN (
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Package Function 48 LQ FP 32 LQ FP
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1.9 Modes of Operation MC9S12VR Fam
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1.11.2 Interrupt Vectors MC9S12VR F
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MC9S12VR Family Reference Manual, R
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Chapter 2 Port Integration Module (
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Port Pin Name 2.3 Memory Map and Re
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Global Address 0x0243 Reserved 0x02
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Global Address 0x0272 Reserved 0x02
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2.3.3 Port E Data Register (PORTE)
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1 Read: Anytime Write: Anytime Tabl
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2.3.10 Port T Data Register (PTT) M
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2.3.12 Port T Data Direction Regist
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2.3.15 Module Routing Register 0 (M
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Table 2-16. PTS Register Field Desc
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2.3.19 Port S Data Direction Regist
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2.3.21 Port S Polarity Select Regis
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MODRR20 MODRR21 TXD0 0 1 1 0 LPTXD
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Table 2-24. PTP Register Field Desc
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2.3.26 Port P Data Direction Regist
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2.3.29 Port P Polarity Select Regis
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2.3.32 Port L Input Register (PTIL)
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3 PTAENL 1-0 PTAL Table 2-34. PTAL
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Page 93 and 94: 2.4.3.4 Port S MC9S12VR Family Refe
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Page 107 and 108: 3.3.2.4 Program Page Index Register
Page 111 and 112: 0x0000 0x0400 0x8000 0xC000 0xFFFF
Page 115 and 116: Chapter 4 S12 Clock, Reset and Powe
Page 121 and 122: 4.1.3 S12CPMU_UHV Block Diagram VSU
Page 123 and 124: 4.2 Signal Description MC9S12VR Fam
Page 125 and 126: 4.3 Memory Map and Registers MC9S12
Page 127 and 128: 4.3.2 Register Descriptions MC9S12V
Page 133 and 134: Table 4-5. CPMUCLKS Descriptions Fi
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Page 141 and 142: Table 4-14. COP Watchdog Rates if C
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Page 159 and 160: 4.3.2.23 Reserved Register CPMUTEST
Page 165 and 166: 4.4.6 System Clock Configurations 4
Page 173 and 174: Chapter 5 Background Debug Module (
Page 175 and 176: 5.1.3 Block Diagram A block diagram
Page 177 and 178: Global Address Register Name 0x3_FF
Page 179 and 180: Register Global Address 0x3_FF06 Fi
Page 181 and 182: • Hardware BACKGROUND command •
Page 183 and 184: 5.4.5 BDM Command Structure Table 5
Page 185 and 186: Hardware Read Hardware Write Firmwa
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BDM Clock (Target MCU) Host Drive t
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5.4.9 SYNC — Request Timed Refere
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Chapter 6 S12S Debug Module (S12SDB
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• 4-stage state sequencer for tra
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6.3.2 Register Descriptions MC9S12V
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Address: 0x0021 Reset POR Read: Any
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6.3.2.4 Debug Control Register2 (DB
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6.3.2.6 Debug Count Register (DBGCN
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6.3.2.7.1 Debug State Control Regis
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6.3.2.7.3 Debug State Control Regis
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Address: 0x0028 Read: DBGACTL if CO
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6.3.2.8.2 Debug Comparator Address
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6.3.2.8.6 Debug Comparator Data Low
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6.4.2.1.2 Comparator B MC9S12VR Fam
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RTI ; The execution flow taking int
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Field2 Bits in Normal and Loop1 Mod
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6.5.6 Scenario 5 MC9S12VR Family Re
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Chapter 7 Interrupt Module (S12SINT
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7.2 External Signal Description The
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Chapter 8 Analog-to-Digital Convert
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8.1.2 Modes of Operation 8.1.2.1 Co
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8.2 Signal Description This section
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8.3.2 Register Descriptions MC9S12V
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8.3.2.3 ATD Control Register 2 (ATD
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Table 8-15. Analog Input Channel Se
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3-0 CC[3:0] 8.3.2.8 ATD Compare Ena
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8.3.2.10 ATD Input Enable Register
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8.3.2.12.2 Right Justified Result D
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Chapter 9 Pulse-Width Modulator (S1
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9.3 Memory Map and Register Definit
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Register Name 0x0016 PWMPER2 2 0x00
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9.3.2.2 PWM Polarity Register (PWMP
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9.3.2.6 PWM Control Register (PWMCT
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Module Base + 0x00006 Read: Anytime
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9.3.2.10 PWM Channel Counter Regist
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• The channel is disabled MC9S12V
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Divide by Prescaler Taps: Bus Clock
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9.4.2 PWM Channel Timers MC9S12VR F
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9.4.2.6 Center Aligned Outputs MC9S
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Clock Source 7 Clock Source 5 Clock
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• For channels 0, 1, 4, and 5 the
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Chapter 10 Serial Communication Int
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10.1.4 Block Diagram MC9S12VR Famil
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10.3.2 Register Descriptions MC9S12
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10.3.2.2 SCI Control Register 1 (SC
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10.3.2.3 SCI Alternative Status Reg
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10.3.2.5 SCI Alternative Control Re
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10.3.2.7 SCI Status Register 1 (SCI
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10.3.2.8 SCI Status Register 2 (SCI
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10.4 Functional Description MC9S12V
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10.4.3 Data Format MC9S12VR Family
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10.4.5 Transmitter Bus Clock SBR12:
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10.4.5.5 LIN Transmit Collision Det
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10.4.6.5.2 Fast Data Tolerance MC9S
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10.5.3.1 Description of Interrupt O
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Chapter 11 Serial Peripheral Interf
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SPI Interrupt Request Bus Clock SPI
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11.3.2 Register Descriptions MC9S12
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Table 11-4. SPICR2 Field Descriptio
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5 SPTEF 4 MODF Table 11-8. SPISR Fi
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Receive Shift Register SPIF SPI Dat
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11.4.3.1 Clock Phase and Polarity C
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NOTE Care must be taken when expect
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Chapter 12 Timer Module (TIM16B8CV3
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12.1.3 Block Diagrams PA input inte
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PULSE ACCUMULATOR CHANNEL 7 OUTPUT
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Register Name 0x000E TFLG1 1 0x000F
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12.3.2.3 Output Compare 7 Mask Regi
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Write: Anytime. 12.3.2.10 Timer Int
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NOTE The newly selected prescale fa
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12.3.2.15 16-Bit Pulse Accumulator
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... MC9S12VR Family Reference Manua
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12.4.1 Prescaler MC9S12VR Family Re
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12.4.5 Event Counter Mode MC9S12VR
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Chapter 13 High-Side Drivers - HSDR
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13.2 External Signal Description Ta
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13.3.2 Register Definition 13.3.3 P
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13.3.5 Reserved Register MC9S12VR F
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13.3.8 HSDRV Interrupt Flag Registe
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13.4.4.1 HSDRV Over Current Interru
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Chapter 14 Low-Side Drivers - LSDRV
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14.2 External Signal Description Ta
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14.3.2 Register Definition 14.3.3 P
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14.3.5 Reserved Register MC9S12VR F
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14.3.7 LSDRV Status Register (LSSR)
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14.3.9 LSDRV Interrupt Flag Registe
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14.4.4.1 LSDRV Over Current Interru
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Chapter 15 LIN Physical Layer (S12L
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IP-BUS LPRXD LPTXD Figure 15-1. LIN
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15.3 Memory Map and Register Defini
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15.3.2.2 LIN Control Register (LPCR
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7 LPSLRWD 1-0 LPSLR[1:0] 15.3.2.5 R
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15.3.2.7 LIN Interrupt Enable Regis
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NOTE For 20kBit/s and Fast Mode com
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15.4.3.2 Normal Mode MC9S12VR Famil
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15.5.2 Use Cases 15.5.2.1 LIN Physi
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Chapter 16 Supply Voltage Sensor -
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16.3.2.1 BATS Module Enable Registe
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16.3.2.2 BATS Module Status Registe
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16.3.2.5 Reserved Register NOTE The
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Chapter 17 64 KByte Flash Module (S
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17.1.2.3 Other Flash Module Feature
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P-Flash Memory Map Global Address S
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Address & Name 0x0003 FRSV0 0x0004
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6 FDIVLCK 5-0 FDIV[5:0] 17.3.2.2 Fl
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The security function in the Flash
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Offset Module Base + 0x0005 All ass
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Table 17-15. FERSTAT Field Descript
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Table 17-19. P-Flash Protection Low
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Scenario FLASH START 0x3_8000 0x3_F
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011 100 101 17.3.2.12 Flash Reserve
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17.3.2.17 Flash Reserved5 Register
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FCCOB Availability Check Clock Divi
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17.4.4.4 P-Flash Commands MC9S12VR
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17.4.6 Flash Command Description MC
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Table 17-35. Erase Verify P-Flash S
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17.4.6.6 Program Once Command Table
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Table 17-44. Erase Flash Block Comm
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17.4.6.13 Set Field Margin Level Co
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Table 17-59. Erase Verify EEPROM Se
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17.4.7 Interrupts MC9S12VR Family R
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Appendix A MCU Electrical Specifica
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A.1.3 Current Injection MC9S12VR Fa
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A.1.5 ESD Protection and Latch-up I
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A.1.6 Operating Conditions MC9S12VR
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VBAT GND Figure A-2. Supply Current
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A.1.8 I/O Characteristics This sect
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Table A-10. CPMU Configuration for
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Appendix B VREG Electrical Specific
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Appendix C ATD Electrical Specifica
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Supply voltage 3.13 V < V DDA < 5.5
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Supply voltage V DDA =5.12 V, -40 o
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Appendix D HSDRV Electrical Specifi
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Appendix E PLL Electrical Specifica
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Appendix F IRC Electrical Specifica
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Appendix G LINPHY Electrical Specif
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Appendix H LSDRV Electrical Specifi
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Appendix I BATS Electrical Specific
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9 D VSENSE Series Resistor Required
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Appendix J PIM Electrical Specifica
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Appendix K SPI Electrical Specifica
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f SCK /f bus 1/2 1/4 5 Figure K-3.
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In Table K-3. the timing characteri
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Appendix L XOSCLCP Electrical Speci
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Appendix M FTMRG Electrical Specifi
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M.1.1 NVM Reliability Parameters Ta
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Appendix N Package Information MC9S
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Appendix O Ordering Information MC9
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Appendix P Detailed Register Addres
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0x001A-0x001B Part ID Registers MC9
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0x0034-0x003F Clock Reset and Power
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0x0070-0x009F Analog to Digital Con
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0x00A0-0x00C7 Pulse Width Modulator
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0x0120 Interrupt Vector Base Regist
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0x0160-0x0167 LIN Physical Layer (L
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0x0240 -0x027F Port Integration Mod
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0x0280-0x02EF Reserved MC9S12VR Fam
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