MC9S12VR-Family - Data Sheet - Freescale Semiconductor

Low-Side Drivers - LSDRV (S12LSDRV1)
• Active clamp to protect the device against over-voltage when the power transistor that is driving an
inductive load (relay) is turned off.
14.1.2 Modes of Operation
The LSDRV module behaves as follows in the system operating modes:
1. Run mode
The activation of the LSE0 or LSE1 bits enable the related low-side driver. The gate is controlled
by the selected source in the Port Integration Module (see PIM chapter).
2. Stop mode
During stop mode operation the low-side drivers are shut down, i.e. the low-side drivers are
disabled and their gates are turned off. The bits in the data register which control the gates (LSDRx)
are cleared automatically. After returning from stop mode the drivers are re-enabled. If the data
register bits (LSDRx) were chosen as source in PIM module, then the respective low-side driver
gates stays turned off until the software sets the associated bit in the data register (LSDRx). When
the timer or PWM were chosen as source, the respective low-side driver gate is controlled by the
timer or PWM without further handling. When it is required that the gate stays turned off after the
stop mode for this case (PWM or timer), the software must take the appropriate action to turn off
the gate before entering stop mode.
14.1.3 Block Diagram
Figure 14-1 shows a block diagram of the LSDRV module. The module consists of a control and an output
stage. Internal functions can be routed to control the low-side drivers. See PIM chapter for routing options.
LS0 control
LS1 control
Figure 14-1. LSDRV Block Diagram
Low Side Driver Control
MC9S12VR Family Reference Manual, Rev. 2.8
LSGND
410 Freescale Semiconductor
LS0
LS1