MC9S12VR-Family - Data Sheet - Freescale Semiconductor

2.4.3.4 Port S
MC9S12VR Family Reference Manual, Rev. 2.8
Port Integration Module (S12VRPIMV2)
This port is associated with the ECLK, SPI, SCI1, routed SCI0, routed PWM channels and ETRIG inputs.
Port S pins can be used either for general-purpose I/O, or with the ECLK, SPI, SCI, and PWM subsystems.
2.4.3.5 Port P
Port P pins can be used for either general-purpose I/O, IRQ and XIRQ or with the PWM subsystem. All
pins feature pin interrupt functionality.
PP2 has an increased current capability to drive up to 20 mA to supply external devices for external Hall
sensors. An over-current protection is available.
PP1 and PP0 have an increased current capability to drive up to 10 mA.
PP4 and PP5 support ETRIG functionality.
PP5 can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ interrupt
input. IRQ will be enabled by setting the IRQCR[IRQEN] configuration bit (2.3.8/2-59) and clearing the
I-bit in the CPU condition code register. It is inhibited at reset so this pin is initially configured as a simple
input with a pullup.
PP0 can be used for either general-purpose input or as the level-sensitive XIRQ interrupt input. XIRQ can
be enabled by clearing the X-bit in the CPU condition code register. It is inhibited at reset so this pin is
initially configured as a high-impedance input with a pullup.
2.4.3.6 Port L
Port L provides four high-voltage inputs (HVI) with the following features:
• Input voltage proof up to VHVIx • Digital input function with pin interrupt and wakeup from stop capability
• Analog input function with selectable divider ratio routable to ADC channel. Optional direct input
bypassing voltage divider and impedance converter. Capable to wakeup from stop (pin interrupts
in run mode not available). Open input detection.
Figure 2-46 shows a block diagram of the HVI.
Freescale Semiconductor 93