MC9S12VR-Family - Data Sheet - Freescale Semiconductor

Port Integration Module (S12VRPIMV2)
2.3.35 Port L Input Divider Ratio Selection Register (PIRL)
Address 0x026C Access: User read/write 1
1 Read: Anytime
Write: Anytime
7 6 5 4 3 2 1 0
R 0 0 0 0
W
2.3.36 Port L Polarity Select Register (PPSL)
MC9S12VR Family Reference Manual, Rev. 2.8
PIRL3 PIRL2 PIRL1 PIRL0
Reset 0 0 0 0 0 0 0 0
Figure 2-34. Port L Input Divider Ratio Selection Register (PIRL)
Table 2-36. PIRL Register Field Descriptions
Field Description
3-0
PIRL
Port L Input Divider Ratio Select —
This bit selects one of two voltage divider ratios for the associated high-voltage input pin in analog mode.
1 Ratio L_HVI selected
0 Ratio H_HVI selected
Address 0x026D Access: User read/write 1
1 Read: Anytime
Write: Anytime
7 6 5 4 3 2 1 0
R 0 0 0 0
W
PPSL3 PPSL2 PPSL1 PPSL0
Reset 0 0 0 0 0 0 0 0
Figure 2-35. Port L Polarity Select Register (PPSL)
Table 2-37. PPSL Register Field Descriptions
Field Description
3-0
PPSL
Pin interrupt Polarity Select register port L —
This bit selects the polarity of the active pin interrupt edge.
1 Rising edge selected
0 Falling edge selected
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