MC9S12VR-Family - Data Sheet - Freescale Semiconductor

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Port Integration Module (S12VRPIMV2) Global Address 0x025A DDRP 0x025B RDRP 0x025C PERP 0x025D PPSP 0x025E PIEP 0x025F PIFP 0x0260– 0x0268 Reserved 0x0269 PTIL 0x026A DIENL 0x026B PTAL 0x026C PIRL 0x026D PPSL 0x026E PIEL 0x026F Register Name PIFL 0x0270 Reserved 0x0271 PT1AD R 0 0 W DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 R 0 0 0 0 0 W R 0 0 W R 0 0 W R W R W OCIE OCIF 0 0 MC9S12VR Family Reference Manual, Rev. 2.8 RDRP2 RDRP1 RDRP0 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 R W 0 0 0 0 0 0 0 0 R W 0 0 0 0 PTIL3 PTIL2 PTIL1 PTIL0 R 0 0 0 0 W R PTTEL PTPSL PTABYPL PTADIRL PTAENL W R 0 0 0 0 W R 0 0 0 0 W R 0 0 0 0 W R 0 0 0 0 W DIENL3 DIENL2 DIENL1 DIENL0 54 Freescale Semiconductor 0 PTAL1 PTAL0 PIRL3 PIRL2 PIRL1 PIRL0 PPSL3 PPSL2 PPSL1 PPSL0 PIEL3 PIEL2 PIEL1 PIEL0 PIFL3 PIFL2 PIFL1 PIFL0 R W 0 0 0 0 0 0 0 0 R 0 0 W Bit 7 6 5 4 3 2 1 Bit 0 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0
Global Address 0x0272 Reserved 0x0273 PTI1AD 0x0274 Reserved 0x0275 DDR1AD 0x0276– 0x0278 Register Name Reserved 0x0279 PER1AD 0x027A Reserved 0x027B PPS1AD 0x027C Reserved 0x027D PIE1AD 0x027E Reserved 0x027F PIF1AD 2.3.2 Register Descriptions MC9S12VR Family Reference Manual, Rev. 2.8 Port Integration Module (S12VRPIMV2) R W 0 0 0 0 0 0 0 0 R 0 0 W PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0 R W 0 0 0 0 0 0 0 0 R 0 0 W DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0 R W 0 0 0 0 0 0 0 0 R 0 0 W PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 R W 0 0 0 0 0 0 0 0 R 0 0 W PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0 R W 0 0 0 0 0 0 0 0 R 0 0 W PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 R W 0 0 0 0 0 0 0 0 R 0 0 W Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0 The following table summarizes the effect of the various configuration bits, that is data direction (DDR), output level (PORT/PT), pull enable (PER), pull select (PPS), interrupt enable (PIE) on the pin function, pull device and interrupt activity. The configuration bit PPS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. Freescale Semiconductor 55
Page 1 and 2:
MC9S12VR-Family Reference Manual S1
Page 3 and 4: Chapter 1 Device Overview MC9S12VR-
Page 7 and 8: 2.3.34 Port L Analog Access Registe
Page 9 and 10: 5.2 External Signal Description . .
Page 11 and 12: Chapter 9 Pulse-Width Modulator (S1
Page 13 and 14: 12.4.6 Gated Time Accumulation Mode
Page 15 and 16: 16.1.2 Modes of Operation . . . . .
Page 17 and 18: Appendix H LSDRV Electrical Specifi
Page 21 and 22: 1.3 Chip-Level Features Feature MC9
Page 23 and 24: 1.4.4 Main External Oscillator (XOS
Page 25 and 26: • Programmable polarity for trans
Page 27 and 28: 1.5 Block Diagram PE0 PE1 VSUP VSS
Page 29 and 30: Address Module NOTE Reserved regist
Page 31 and 32: 1.6.1 Part ID Assignments MC9S12VR
Page 33 and 34: 1.7.2.7 PS[5:0] — Port S I/O Sign
Page 35 and 36: 1.7.2.21 IOC[3:0] Signals MC9S12VR
Page 37 and 38: 1.8.1 Pinout 48-pin LQFP LGND LIN (
Page 39 and 40: Package Function 48 LQ FP 32 LQ FP
Page 41 and 42: 1.9 Modes of Operation MC9S12VR Fam
Page 43 and 44: 1.11.2 Interrupt Vectors MC9S12VR F
Page 45 and 46: MC9S12VR Family Reference Manual, R
Page 47 and 48: Chapter 2 Port Integration Module (
Page 51 and 52: Port Pin Name 2.3 Memory Map and Re
Page 53: Global Address 0x0243 Reserved 0x02
Page 57 and 58: 2.3.3 Port E Data Register (PORTE)
Page 59 and 60: 1 Read: Anytime Write: Anytime Tabl
Page 61 and 62: 2.3.10 Port T Data Register (PTT) M
Page 63 and 64: 2.3.12 Port T Data Direction Regist
Page 65 and 66: 2.3.15 Module Routing Register 0 (M
Page 67 and 68: Table 2-16. PTS Register Field Desc
Page 69 and 70: 2.3.19 Port S Data Direction Regist
Page 71 and 72: 2.3.21 Port S Polarity Select Regis
Page 73 and 74: MODRR20 MODRR21 TXD0 0 1 1 0 LPTXD
Page 75 and 76: Table 2-24. PTP Register Field Desc
Page 77 and 78: 2.3.26 Port P Data Direction Regist
Page 79 and 80: 2.3.29 Port P Polarity Select Regis
Page 81 and 82: 2.3.32 Port L Input Register (PTIL)
Page 83 and 84: 3 PTAENL 1-0 PTAL Table 2-34. PTAL
Page 85 and 86: 2.3.37 Port L Interrupt Enable Regi
Page 87 and 88: 2.3.41 Port AD Data Direction Regis
Page 89 and 90: 2.3.44 Port AD Interrupt Enable Reg
Page 93 and 94: 2.4.3.4 Port S MC9S12VR Family Refe
Page 97 and 98: Glitch, filtered out, no interrupt
Page 99 and 100: 110K / 550K PIRL=0 / PIRL=1 HV Supp
Page 101 and 102: Chapter 3 S12G Memory Map Controlle
Page 103 and 104: 3.2 External Signal Description Fig
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Read: Anytime. Write: Only if a tra
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3.3.2.4 Program Page Index Register
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MC9S12VR Family Reference Manual, R
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0x0000 0x0400 0x8000 0xC000 0xFFFF
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Chapter 4 S12 Clock, Reset and Powe
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4.1.3 S12CPMU_UHV Block Diagram VSU
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4.2 Signal Description MC9S12VR Fam
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4.3 Memory Map and Registers MC9S12
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4.3.2 Register Descriptions MC9S12V
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Table 4-5. CPMUCLKS Descriptions Fi
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4.3.2.7 S12CPMU_UHV PLL Control Reg
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RTR[3:0] 0000 (÷1) 000 (OFF) OFF 1
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4.3.2.9 S12CPMU_UHV COP Control Reg
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Table 4-14. COP Watchdog Rates if C
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4.3.2.14 Low Voltage Control Regist
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APIES=0 APIES=1 MC9S12VR Family Ref
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4.3.2.18 Reserved Register CPMUTEST
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frequency MC9S12VR Family Reference
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4.3.2.23 Reserved Register CPMUTEST
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4.4.6 System Clock Configurations 4
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Chapter 5 Background Debug Module (
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5.1.3 Block Diagram A block diagram
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Global Address Register Name 0x3_FF
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Register Global Address 0x3_FF06 Fi
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• Hardware BACKGROUND command •
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5.4.5 BDM Command Structure Table 5
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Hardware Read Hardware Write Firmwa
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BDM Clock (Target MCU) Host Drive t
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5.4.9 SYNC — Request Timed Refere
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Chapter 6 S12S Debug Module (S12SDB
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• 4-stage state sequencer for tra
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Address: 0x0021 Reset POR Read: Any
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6.3.2.4 Debug Control Register2 (DB
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6.3.2.6 Debug Count Register (DBGCN
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6.3.2.7.1 Debug State Control Regis
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6.3.2.7.3 Debug State Control Regis
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Address: 0x0028 Read: DBGACTL if CO
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6.3.2.8.2 Debug Comparator Address
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6.3.2.8.6 Debug Comparator Data Low
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6.4.2.1.2 Comparator B MC9S12VR Fam
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RTI ; The execution flow taking int
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Field2 Bits in Normal and Loop1 Mod
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6.5.6 Scenario 5 MC9S12VR Family Re
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Chapter 7 Interrupt Module (S12SINT
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7.2 External Signal Description The
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Chapter 8 Analog-to-Digital Convert
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8.1.2 Modes of Operation 8.1.2.1 Co
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8.2 Signal Description This section
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8.3.2.3 ATD Control Register 2 (ATD
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Table 8-15. Analog Input Channel Se
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3-0 CC[3:0] 8.3.2.8 ATD Compare Ena
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8.3.2.10 ATD Input Enable Register
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8.3.2.12.2 Right Justified Result D
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Chapter 9 Pulse-Width Modulator (S1
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9.3 Memory Map and Register Definit
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Register Name 0x0016 PWMPER2 2 0x00
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9.3.2.2 PWM Polarity Register (PWMP
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9.3.2.6 PWM Control Register (PWMCT
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Module Base + 0x00006 Read: Anytime
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9.3.2.10 PWM Channel Counter Regist
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• The channel is disabled MC9S12V
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Divide by Prescaler Taps: Bus Clock
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9.4.2 PWM Channel Timers MC9S12VR F
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9.4.2.6 Center Aligned Outputs MC9S
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Clock Source 7 Clock Source 5 Clock
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• For channels 0, 1, 4, and 5 the
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Chapter 10 Serial Communication Int
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10.1.4 Block Diagram MC9S12VR Famil
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10.3.2 Register Descriptions MC9S12
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10.3.2.2 SCI Control Register 1 (SC
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10.3.2.3 SCI Alternative Status Reg
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10.3.2.5 SCI Alternative Control Re
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10.3.2.7 SCI Status Register 1 (SCI
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10.3.2.8 SCI Status Register 2 (SCI
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10.4 Functional Description MC9S12V
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10.4.3 Data Format MC9S12VR Family
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10.4.5 Transmitter Bus Clock SBR12:
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10.4.5.5 LIN Transmit Collision Det
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10.4.6.5.2 Fast Data Tolerance MC9S
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10.5.3.1 Description of Interrupt O
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Chapter 11 Serial Peripheral Interf
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SPI Interrupt Request Bus Clock SPI
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11.3.2 Register Descriptions MC9S12
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Table 11-4. SPICR2 Field Descriptio
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5 SPTEF 4 MODF Table 11-8. SPISR Fi
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Receive Shift Register SPIF SPI Dat
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11.4.3.1 Clock Phase and Polarity C
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NOTE Care must be taken when expect
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Chapter 12 Timer Module (TIM16B8CV3
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12.1.3 Block Diagrams PA input inte
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PULSE ACCUMULATOR CHANNEL 7 OUTPUT
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Register Name 0x000E TFLG1 1 0x000F
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12.3.2.3 Output Compare 7 Mask Regi
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Write: Anytime. 12.3.2.10 Timer Int
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NOTE The newly selected prescale fa
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12.3.2.15 16-Bit Pulse Accumulator
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... MC9S12VR Family Reference Manua
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12.4.1 Prescaler MC9S12VR Family Re
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12.4.5 Event Counter Mode MC9S12VR
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Chapter 13 High-Side Drivers - HSDR
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13.2 External Signal Description Ta
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13.3.2 Register Definition 13.3.3 P
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13.3.5 Reserved Register MC9S12VR F
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13.3.8 HSDRV Interrupt Flag Registe
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13.4.4.1 HSDRV Over Current Interru
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Chapter 14 Low-Side Drivers - LSDRV
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14.2 External Signal Description Ta
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14.3.2 Register Definition 14.3.3 P
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14.3.5 Reserved Register MC9S12VR F
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14.3.7 LSDRV Status Register (LSSR)
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14.3.9 LSDRV Interrupt Flag Registe
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14.4.4.1 LSDRV Over Current Interru
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Chapter 15 LIN Physical Layer (S12L
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IP-BUS LPRXD LPTXD Figure 15-1. LIN
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15.3 Memory Map and Register Defini
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15.3.2.2 LIN Control Register (LPCR
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7 LPSLRWD 1-0 LPSLR[1:0] 15.3.2.5 R
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15.3.2.7 LIN Interrupt Enable Regis
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NOTE For 20kBit/s and Fast Mode com
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15.4.3.2 Normal Mode MC9S12VR Famil
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15.5.2 Use Cases 15.5.2.1 LIN Physi
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Chapter 16 Supply Voltage Sensor -
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16.3.2.1 BATS Module Enable Registe
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16.3.2.2 BATS Module Status Registe
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16.3.2.5 Reserved Register NOTE The
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Chapter 17 64 KByte Flash Module (S
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17.1.2.3 Other Flash Module Feature
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P-Flash Memory Map Global Address S
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Address & Name 0x0003 FRSV0 0x0004
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6 FDIVLCK 5-0 FDIV[5:0] 17.3.2.2 Fl
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The security function in the Flash
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Offset Module Base + 0x0005 All ass
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Table 17-15. FERSTAT Field Descript
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Table 17-19. P-Flash Protection Low
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Scenario FLASH START 0x3_8000 0x3_F
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011 100 101 17.3.2.12 Flash Reserve
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17.3.2.17 Flash Reserved5 Register
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FCCOB Availability Check Clock Divi
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17.4.4.4 P-Flash Commands MC9S12VR
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17.4.6 Flash Command Description MC
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Table 17-35. Erase Verify P-Flash S
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17.4.6.6 Program Once Command Table
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Table 17-44. Erase Flash Block Comm
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17.4.6.13 Set Field Margin Level Co
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Table 17-59. Erase Verify EEPROM Se
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17.4.7 Interrupts MC9S12VR Family R
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Appendix A MCU Electrical Specifica
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A.1.3 Current Injection MC9S12VR Fa
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A.1.5 ESD Protection and Latch-up I
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A.1.6 Operating Conditions MC9S12VR
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VBAT GND Figure A-2. Supply Current
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A.1.8 I/O Characteristics This sect
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Table A-10. CPMU Configuration for
Page 519 and 520:
Appendix B VREG Electrical Specific
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Appendix C ATD Electrical Specifica
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Supply voltage 3.13 V < V DDA < 5.5
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Supply voltage V DDA =5.12 V, -40 o
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Appendix D HSDRV Electrical Specifi
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Appendix E PLL Electrical Specifica
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Appendix F IRC Electrical Specifica
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Appendix G LINPHY Electrical Specif
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Appendix H LSDRV Electrical Specifi
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Appendix I BATS Electrical Specific
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9 D VSENSE Series Resistor Required
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Appendix J PIM Electrical Specifica
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Appendix K SPI Electrical Specifica
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f SCK /f bus 1/2 1/4 5 Figure K-3.
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In Table K-3. the timing characteri
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Appendix L XOSCLCP Electrical Speci
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Appendix M FTMRG Electrical Specifi
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M.1.1 NVM Reliability Parameters Ta
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Appendix N Package Information MC9S
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Page 563 and 564:
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Appendix O Ordering Information MC9
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Appendix P Detailed Register Addres
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0x001A-0x001B Part ID Registers MC9
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0x0034-0x003F Clock Reset and Power
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0x0070-0x009F Analog to Digital Con
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0x00A0-0x00C7 Pulse Width Modulator
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0x0120 Interrupt Vector Base Regist
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0x0160-0x0167 LIN Physical Layer (L
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0x0240 -0x027F Port Integration Mod
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0x0280-0x02EF Reserved MC9S12VR Fam
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