MC9S12VR-Family - Data Sheet - Freescale Semiconductor

Serial Peripheral Interface (S12SPIV5)
End of Idle State Begin Transfer
End
Begin of Idle State
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
MOSI pin
CHANGE O
MISO pin
SEL SS (O)
Master only
SEL SS (I)
MSB first (LSBFE = 0):
LSB first (LSBFE = 1):
t L
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Figure 11-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0)
MC9S12VR Family Reference Manual, Rev. 2.8
360 Freescale Semiconductor
Bit 3
Bit 4
Bit 2
Bit 5
t L = Minimum leading time before the first SCK edge
t T = Minimum trailing time after the last SCK edge
t I = Minimum idling time between transfers (minimum SS high time)
t L , t T , and t I are guaranteed for the master mode and required for the slave mode.
Bit 1
Bit 6
LSB
MSB
t T
t I
t L
If next transfer begins here
Minimum 1/2 SCK
for tT , tl , tL