MC9S12VR-Family - Data Sheet - Freescale Semiconductor

6.3.2.8.6 Debug Comparator Data Low Register (DBGADL)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed.
6.3.2.8.7 Debug Comparator Data High Mask Register (DBGADHM)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG not armed.
Table 6-28. DBGADH Field Descriptions
Field Description
7–0
Bits[15:8]
Address: 0x002D
MC9S12VR Family Reference Manual, Rev. 2.8
S12S Debug Module (S12SDBGV2)
Comparator Data High Compare Bits— The Comparator data high compare bits control whether the selected
comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear.
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
7 6 5 4 3 2 1 0
R
W
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset 0 0 0 0 0 0 0 0
Figure 6-20. Debug Comparator Data Low Register (DBGADL)
Table 6-29. DBGADL Field Descriptions
Field Description
7–0
Bits[7:0]
Address: 0x002E
Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected
comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
7 6 5 4 3 2 1 0
R
W
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reset 0 0 0 0 0 0 0 0
Figure 6-21. Debug Comparator Data High Mask Register (DBGADHM)
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