MC9S12VR-Family - Data Sheet - Freescale Semiconductor

Port Integration Module (S12VRPIMV2)
MODRR2[3:0] Signal Routing Description
1100
Probe setting:
SCI0 connects to LINPHY, interface accessible on 2 external pins
1110
Conformance test setting:
Interface opened and all 4 signals routed externally
NOTE
For standalone usage of SCI0 on external pins set MODRR2[3:0]=0b1110
and disable the LINPHY (LPCR[LPE]=0). This releases PT2 and PT3 to
other associated functions and maintains TXD0 and RXD0 signals on PT1
and PT0, respectively, if no other function with higher priority takes
precedence.
2.3.24 Port P Data Register (PTP)
Address 0x0258 Access: User read/write 1
7 6 5 4 3 2 1 0
R 0 0
W
Altern.
Function
— — PWM5 23
PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
PWM4 23
PWM3 2
1 Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
2
PWM function available on this pin only if not used with a routed HSDRV or LSDRV function. Refer to Section 2.3.15, “Module
Routing Register 0 (MODRR0)”
3 PWM function available on this pin only if not routed to port S. Refer to Section 2.3.16, “Module Routing Register 1 (MODRR1)”
MC9S12VR Family Reference Manual, Rev. 2.8
PWM2 PWM1 2
— — IRQ — — EVDD XIRQ —
— — ETRIG1 ETRIG0 — — — —
Reset 0 0 0 0 0 0 0 0
Figure 2-23. Port P Data Register (PTP)
PWM0
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