MC9S12VR-Family - Data Sheet - Freescale Semiconductor

Address Module
NOTE
Reserved register space shown in Table 1-3 is not allocated to any module.
This register space is reserved for future use. Writing to these locations has
no effect. Read access to these locations returns zero.
MC9S12VR Family Reference Manual, Rev. 2.8
Device Overview MC9S12VR-Family
Size
(Bytes)
0x0280–0x02EF Reserved 112
0x02F0–0x02FF CPMU (clock and power management) 16
0x0300–0x03FF Reserved 256
Figure 1-2 shows MC9S12VR-Family CPU and BDM local address translation to the global memory map
as a graphical representation. The whole 256K global memory space is visible through the P-Flash window
located in the 64k local memory map located at 0x8000 - 0xBFFF using the PPAGE register.
NOTE
Flash space on page 0xC in Figure 1-2 is not available on S12VR48. This is
only available on S12VR64.
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