MC9S12VR-Family - Data Sheet - Freescale Semiconductor

1.11.2 Interrupt Vectors
MC9S12VR Family Reference Manual, Rev. 2.8
Device Overview MC9S12VR-Family
$FFFA COP watchdog reset None CR[2:0] in CPMUCOP register
Table 1-10 lists all interrupt sources and vectors in the default order of priority. The interrupt module (see
Chapter 7, “Interrupt Module (S12SINTV1)”) provides an interrupt vector base register (IVBR) to relocate
the vectors.
Table 1-10. Interrupt Vector Locations (Sheet 1 of 2)
Vector Address 1
Interrupt Source
CCR
Mask
Local Enable
Wake up
from STOP
Wake up
from WAIT
Vector base + $F8 Unimplemented instruction trap None None - -
Vector base+ $F6 SWI None None - -
Vector base+ $F4 XIRQ X Bit None Yes Yes
Vector base+ $F2 IRQ I bit IRQCR (IRQEN) Yes Yes
Vector base+ $F0 RTI time-out interrupt I bit CPMUINT (RTIE) 4.6 Interrupts
Vector base+ $EE TIM timer channel 0 I bit TIE (C0I) No Yes
Vector base + $EC TIM timer channel 1 I bit TIE (C1I) No Yes
Vector base+ $EA TIM timer channel 2 I bit TIE (C2I) No Yes
Vector base+ $E8 TIM timer channel 3 I bit TIE (C3I) No Yes
Vector base+ $E6
to
Vector base + $E0
Reserved
Vector base+ $DE TIM timer overflow I bit TSCR2(TOF) No Yes
Vector base+ $DC
to
Vector base + $DA
Vector Address Reset Source
Reserved
Vector base + $D8 SPI I bit SPICR1 (SPIE, SPTIE) No Yes
Vector base+ $D6 SCI0 I bit SCI0CR2
(TIE, TCIE, RIE, ILIE)
Vector base + $D4 SCI1 I bit SCI1CR2
(TIE, TCIE, RIE, ILIE)
Yes Yes
Yes Yes
Vector base + $D2 ADC I bit ATDCTL2 (ASCIE) No Yes
Vector base + $D0 Reserved
CCR
Mask
Local Enable
Vector base + $CE Port L I bit PIEL (PIEL3-PIEL0) Yes Yes
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