MC9S12VR-Family - Data Sheet - Freescale Semiconductor

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64 KByte Flash Module (S12FTMRG64K512V1) 17.4.6.2 Erase Verify Block Command The Erase Verify Block command allows the user to verify that an entire P-Flash or EEPROM block has been erased. The FCCOB global address bits determine which block must be verified. Table 17-32. Erase Verify Block Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x02 Upon clearing CCIF to launch the Erase Verify Block command, the Memory Controller will verify that the selected P-Flash or EEPROM block is erased. The CCIF flag will set after the Erase Verify Block operation has completed.If the block is not erased, it means blank check failed, both MGSTAT bits will be set. 17.4.6.3 Erase Verify P-Flash Section Command Global address [17:16] of the Flash block to be verified. Table 17-33. Erase Verify Block Command Error Handling Register Error Bit Error Condition FSTAT ACCERR FPVIOL None Set if CCOBIX[2:0] != 000 at command launch Set if an invalid global address [17:16] is supplied MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. The Erase Verify P-Flash Section command will verify that a section of code in the P-Flash memory is erased. The Erase Verify P-Flash Section command defines the starting point of the code to be verified and the number of phrases. Table 17-34. Erase Verify P-Flash Section Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x03 Global address [17:16] of a P-Flash block 001 Global address [15:0] of the first phrase to be verified 010 Number of phrases to be verified Upon clearing CCIF to launch the Erase Verify P-Flash Section command, the Memory Controller will verify the selected section of Flash memory is erased. The CCIF flag will set after the Erase Verify P-Flash Section operation has completed. If the section is not erased, it means blank check failed, both MGSTAT bits will be set. MC9S12VR Family Reference Manual, Rev. 2.8 490 Freescale Semiconductor
Table 17-35. Erase Verify P-Flash Section Command Error Handling Register Error Bit Error Condition FSTAT ACCERR FPVIOL None 17.4.6.4 Read Once Command Set if CCOBIX[2:0] != 010 at command launch MC9S12VR Family Reference Manual, Rev. 2.8 64 KByte Flash Module (S12FTMRG64K512V1) Set if command not available in current mode (see Table 17-26) Set if an invalid global address [17:0] is supplied see ) Set if a misaligned phrase address is supplied (global address [2:0] != 000) Set if the requested section crosses a the P-Flash address boundary MGSTAT1 Set if any errors have been encountered during the read or if blank check failed. MGSTAT0 Set if any non-correctable errors have been encountered during the read or if blank check failed. The Read Once command provides read access to a reserved 64 byte field (8 phrases) located in the nonvolatile information register of P-Flash. The Read Once field is programmed using the Program Once command described in Section 17.4.6.6. The Read Once command must not be executed from the Flash block containing the Program Once reserved field to avoid code runaway. Table 17-36. Read Once Command FCCOB Requirements CCOBIX[2:0] FCCOB Parameters 000 0x04 Not Required 001 Read Once phrase index (0x0000 - 0x0007) 010 Read Once word 0 value 011 Read Once word 1 value 100 Read Once word 2 value 101 Read Once word 3 value Upon clearing CCIF to launch the Read Once command, a Read Once phrase is fetched and stored in the FCCOB indexed register. The CCIF flag will set after the Read Once operation has completed. Valid phrase index values for the Read Once command range from 0x0000 to 0x0007. During execution of the Read Once command, any attempt to read addresses within P-Flash block will return invalid data. Freescale Semiconductor 491
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MC9S12VR-Family Reference Manual S1
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Chapter 1 Device Overview MC9S12VR-
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2.3.34 Port L Analog Access Registe
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5.2 External Signal Description . .
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Chapter 9 Pulse-Width Modulator (S1
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12.4.6 Gated Time Accumulation Mode
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16.1.2 Modes of Operation . . . . .
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Appendix H LSDRV Electrical Specifi
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1.3 Chip-Level Features Feature MC9
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1.4.4 Main External Oscillator (XOS
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• Programmable polarity for trans
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1.5 Block Diagram PE0 PE1 VSUP VSS
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Address Module NOTE Reserved regist
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1.6.1 Part ID Assignments MC9S12VR
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1.7.2.7 PS[5:0] — Port S I/O Sign
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1.7.2.21 IOC[3:0] Signals MC9S12VR
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1.8.1 Pinout 48-pin LQFP LGND LIN (
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Package Function 48 LQ FP 32 LQ FP
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1.9 Modes of Operation MC9S12VR Fam
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1.11.2 Interrupt Vectors MC9S12VR F
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MC9S12VR Family Reference Manual, R
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Chapter 2 Port Integration Module (
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Port Pin Name 2.3 Memory Map and Re
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Global Address 0x0243 Reserved 0x02
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Global Address 0x0272 Reserved 0x02
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2.3.3 Port E Data Register (PORTE)
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1 Read: Anytime Write: Anytime Tabl
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2.3.10 Port T Data Register (PTT) M
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2.3.12 Port T Data Direction Regist
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2.3.15 Module Routing Register 0 (M
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Table 2-16. PTS Register Field Desc
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2.3.19 Port S Data Direction Regist
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2.3.21 Port S Polarity Select Regis
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MODRR20 MODRR21 TXD0 0 1 1 0 LPTXD
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Table 2-24. PTP Register Field Desc
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2.3.26 Port P Data Direction Regist
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2.3.29 Port P Polarity Select Regis
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2.3.32 Port L Input Register (PTIL)
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3 PTAENL 1-0 PTAL Table 2-34. PTAL
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2.3.37 Port L Interrupt Enable Regi
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2.3.41 Port AD Data Direction Regis
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2.3.44 Port AD Interrupt Enable Reg
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2.4.3.4 Port S MC9S12VR Family Refe
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Glitch, filtered out, no interrupt
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110K / 550K PIRL=0 / PIRL=1 HV Supp
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Chapter 3 S12G Memory Map Controlle
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3.2 External Signal Description Fig
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Read: Anytime. Write: Only if a tra
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3.3.2.4 Program Page Index Register
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0x0000 0x0400 0x8000 0xC000 0xFFFF
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Chapter 4 S12 Clock, Reset and Powe
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4.1.3 S12CPMU_UHV Block Diagram VSU
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4.2 Signal Description MC9S12VR Fam
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4.3 Memory Map and Registers MC9S12
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4.3.2 Register Descriptions MC9S12V
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Table 4-5. CPMUCLKS Descriptions Fi
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4.3.2.7 S12CPMU_UHV PLL Control Reg
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RTR[3:0] 0000 (÷1) 000 (OFF) OFF 1
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4.3.2.9 S12CPMU_UHV COP Control Reg
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Table 4-14. COP Watchdog Rates if C
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4.3.2.14 Low Voltage Control Regist
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APIES=0 APIES=1 MC9S12VR Family Ref
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4.3.2.18 Reserved Register CPMUTEST
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frequency MC9S12VR Family Reference
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4.3.2.23 Reserved Register CPMUTEST
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4.4.6 System Clock Configurations 4
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Chapter 5 Background Debug Module (
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5.1.3 Block Diagram A block diagram
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Global Address Register Name 0x3_FF
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Register Global Address 0x3_FF06 Fi
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• Hardware BACKGROUND command •
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5.4.5 BDM Command Structure Table 5
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Hardware Read Hardware Write Firmwa
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BDM Clock (Target MCU) Host Drive t
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5.4.9 SYNC — Request Timed Refere
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Chapter 6 S12S Debug Module (S12SDB
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• 4-stage state sequencer for tra
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Address: 0x0021 Reset POR Read: Any
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6.3.2.4 Debug Control Register2 (DB
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6.3.2.6 Debug Count Register (DBGCN
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6.3.2.7.1 Debug State Control Regis
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6.3.2.7.3 Debug State Control Regis
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Address: 0x0028 Read: DBGACTL if CO
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6.3.2.8.2 Debug Comparator Address
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6.3.2.8.6 Debug Comparator Data Low
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6.4.2.1.2 Comparator B MC9S12VR Fam
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RTI ; The execution flow taking int
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Field2 Bits in Normal and Loop1 Mod
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6.5.6 Scenario 5 MC9S12VR Family Re
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Chapter 7 Interrupt Module (S12SINT
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7.2 External Signal Description The
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Chapter 8 Analog-to-Digital Convert
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8.1.2 Modes of Operation 8.1.2.1 Co
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8.2 Signal Description This section
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8.3.2.3 ATD Control Register 2 (ATD
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Table 8-15. Analog Input Channel Se
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3-0 CC[3:0] 8.3.2.8 ATD Compare Ena
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8.3.2.10 ATD Input Enable Register
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8.3.2.12.2 Right Justified Result D
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Chapter 9 Pulse-Width Modulator (S1
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9.3 Memory Map and Register Definit
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Register Name 0x0016 PWMPER2 2 0x00
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9.3.2.2 PWM Polarity Register (PWMP
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9.3.2.6 PWM Control Register (PWMCT
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Module Base + 0x00006 Read: Anytime
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9.3.2.10 PWM Channel Counter Regist
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• The channel is disabled MC9S12V
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Divide by Prescaler Taps: Bus Clock
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9.4.2 PWM Channel Timers MC9S12VR F
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9.4.2.6 Center Aligned Outputs MC9S
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Clock Source 7 Clock Source 5 Clock
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• For channels 0, 1, 4, and 5 the
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Chapter 10 Serial Communication Int
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10.1.4 Block Diagram MC9S12VR Famil
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10.3.2 Register Descriptions MC9S12
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10.3.2.2 SCI Control Register 1 (SC
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10.3.2.3 SCI Alternative Status Reg
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10.3.2.5 SCI Alternative Control Re
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10.3.2.7 SCI Status Register 1 (SCI
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10.3.2.8 SCI Status Register 2 (SCI
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10.4 Functional Description MC9S12V
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10.4.3 Data Format MC9S12VR Family
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10.4.5 Transmitter Bus Clock SBR12:
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10.4.5.5 LIN Transmit Collision Det
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10.4.6.5.2 Fast Data Tolerance MC9S
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10.5.3.1 Description of Interrupt O
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Chapter 11 Serial Peripheral Interf
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SPI Interrupt Request Bus Clock SPI
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11.3.2 Register Descriptions MC9S12
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Table 11-4. SPICR2 Field Descriptio
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5 SPTEF 4 MODF Table 11-8. SPISR Fi
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Receive Shift Register SPIF SPI Dat
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11.4.3.1 Clock Phase and Polarity C
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NOTE Care must be taken when expect
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Chapter 12 Timer Module (TIM16B8CV3
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12.1.3 Block Diagrams PA input inte
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PULSE ACCUMULATOR CHANNEL 7 OUTPUT
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Register Name 0x000E TFLG1 1 0x000F
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12.3.2.3 Output Compare 7 Mask Regi
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Write: Anytime. 12.3.2.10 Timer Int
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NOTE The newly selected prescale fa
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12.3.2.15 16-Bit Pulse Accumulator
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... MC9S12VR Family Reference Manua
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12.4.1 Prescaler MC9S12VR Family Re
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12.4.5 Event Counter Mode MC9S12VR
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Chapter 13 High-Side Drivers - HSDR
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13.2 External Signal Description Ta
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13.3.2 Register Definition 13.3.3 P
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13.3.5 Reserved Register MC9S12VR F
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13.3.8 HSDRV Interrupt Flag Registe
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13.4.4.1 HSDRV Over Current Interru
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Chapter 14 Low-Side Drivers - LSDRV
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14.2 External Signal Description Ta
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14.3.2 Register Definition 14.3.3 P
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14.3.5 Reserved Register MC9S12VR F
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14.3.7 LSDRV Status Register (LSSR)
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14.3.9 LSDRV Interrupt Flag Registe
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14.4.4.1 LSDRV Over Current Interru
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Chapter 15 LIN Physical Layer (S12L
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IP-BUS LPRXD LPTXD Figure 15-1. LIN
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15.3 Memory Map and Register Defini
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15.3.2.2 LIN Control Register (LPCR
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7 LPSLRWD 1-0 LPSLR[1:0] 15.3.2.5 R
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15.3.2.7 LIN Interrupt Enable Regis
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NOTE For 20kBit/s and Fast Mode com
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15.4.3.2 Normal Mode MC9S12VR Famil
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Page 443 and 444: 16.3.2.1 BATS Module Enable Registe
Page 445 and 446: 16.3.2.2 BATS Module Status Registe
Page 447 and 448: 16.3.2.5 Reserved Register NOTE The
Page 453 and 454: Chapter 17 64 KByte Flash Module (S
Page 455 and 456: 17.1.2.3 Other Flash Module Feature
Page 459 and 460: P-Flash Memory Map Global Address S
Page 461 and 462: Address & Name 0x0003 FRSV0 0x0004
Page 463 and 464: 6 FDIVLCK 5-0 FDIV[5:0] 17.3.2.2 Fl
Page 465 and 466: The security function in the Flash
Page 467 and 468: Offset Module Base + 0x0005 All ass
Page 469 and 470: Table 17-15. FERSTAT Field Descript
Page 471 and 472: Table 17-19. P-Flash Protection Low
Page 473 and 474: Scenario FLASH START 0x3_8000 0x3_F
Page 477 and 478: 011 100 101 17.3.2.12 Flash Reserve
Page 479 and 480: 17.3.2.17 Flash Reserved5 Register
Page 483 and 484: FCCOB Availability Check Clock Divi
Page 485 and 486: 17.4.4.4 P-Flash Commands MC9S12VR
Page 487: 17.4.6 Flash Command Description MC
Page 491 and 492: 17.4.6.6 Program Once Command Table
Page 493 and 494: Table 17-44. Erase Flash Block Comm
Page 497 and 498: 17.4.6.13 Set Field Margin Level Co
Page 499 and 500: Table 17-59. Erase Verify EEPROM Se
Page 501 and 502: 17.4.7 Interrupts MC9S12VR Family R
Page 505 and 506: Appendix A MCU Electrical Specifica
Page 507 and 508: A.1.3 Current Injection MC9S12VR Fa
Page 509 and 510: A.1.5 ESD Protection and Latch-up I
Page 511 and 512: A.1.6 Operating Conditions MC9S12VR
Page 513 and 514: VBAT GND Figure A-2. Supply Current
Page 515 and 516: A.1.8 I/O Characteristics This sect
Page 517 and 518: Table A-10. CPMU Configuration for
Page 519 and 520: Appendix B VREG Electrical Specific
Page 521 and 522: Appendix C ATD Electrical Specifica
Page 523 and 524: Supply voltage 3.13 V < V DDA < 5.5
Page 525 and 526: Supply voltage V DDA =5.12 V, -40 o
Page 527 and 528: Appendix D HSDRV Electrical Specifi
Page 529 and 530: Appendix E PLL Electrical Specifica
Page 533 and 534: Appendix F IRC Electrical Specifica
Page 535 and 536: Appendix G LINPHY Electrical Specif
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Appendix H LSDRV Electrical Specifi
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Appendix I BATS Electrical Specific
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9 D VSENSE Series Resistor Required
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Appendix J PIM Electrical Specifica
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Appendix K SPI Electrical Specifica
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f SCK /f bus 1/2 1/4 5 Figure K-3.
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In Table K-3. the timing characteri
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Appendix L XOSCLCP Electrical Speci
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Appendix M FTMRG Electrical Specifi
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M.1.1 NVM Reliability Parameters Ta
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Appendix N Package Information MC9S
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Appendix O Ordering Information MC9
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Appendix P Detailed Register Addres
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0x001A-0x001B Part ID Registers MC9
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0x0034-0x003F Clock Reset and Power
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0x0070-0x009F Analog to Digital Con
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0x00A0-0x00C7 Pulse Width Modulator
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0x0120 Interrupt Vector Base Regist
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0x0160-0x0167 LIN Physical Layer (L
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0x0240 -0x027F Port Integration Mod
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0x0280-0x02EF Reserved MC9S12VR Fam
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